22 		writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));  in lpddr2_config_iomux()
24 		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));  in lpddr2_config_iomux()
25 		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));  in lpddr2_config_iomux()
27 		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));  in lpddr2_config_iomux()
28 		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));  in lpddr2_config_iomux()
31 			writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));  in lpddr2_config_iomux()
34 			writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));  in lpddr2_config_iomux()
37 			writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));  in lpddr2_config_iomux()
40 			writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));  in lpddr2_config_iomux()
43 		writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));  in lpddr2_config_iomux()
45 		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));  in lpddr2_config_iomux()
46 		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));  in lpddr2_config_iomux()
48 		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));  in lpddr2_config_iomux()
49 		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));  in lpddr2_config_iomux()
52 			writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));  in lpddr2_config_iomux()
55 			writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));  in lpddr2_config_iomux()
58 			writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));  in lpddr2_config_iomux()
61 			writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));  in lpddr2_config_iomux()
70 	writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);  in config_mmdc()
72 	writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);  in config_mmdc()
73 	writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);  in config_mmdc()
74 	writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);  in config_mmdc()
75 	writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);  in config_mmdc()
76 	writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);  in config_mmdc()
77 	writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);  in config_mmdc()
78 	writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);  in config_mmdc()
79 	writel(_MDCTL, mmdc_addr + MMDC_MDCTL);  in config_mmdc()
81 	writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);  in config_mmdc()
86 	writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);  in config_mmdc()
89 	writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);  in config_mmdc()
90 	writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);  in config_mmdc()
95 	writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);  in config_mmdc()
98 	writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);  in config_mmdc()
99 	writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);  in config_mmdc()
100 	writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);  in config_mmdc()
101 	writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);  in config_mmdc()
108 		writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);  in config_mmdc()
109 		writel(MMDC_MPRDDLCTL_MODULE0_VALUE,  in config_mmdc()
111 		writel(MMDC_MPWRDLCTL_MODULE0_VALUE,  in config_mmdc()
113 		writel(MMDC_MPDGCTRL0_MODULE0_VALUE,  in config_mmdc()
115 		writel(MMDC_MPDGCTRL1_MODULE0_VALUE,  in config_mmdc()
119 		writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);  in config_mmdc()
120 		writel(MMDC_MPRDDLCTL_MODULE1_VALUE,  in config_mmdc()
122 		writel(MMDC_MPWRDLCTL_MODULE1_VALUE,  in config_mmdc()
124 		writel(MMDC_MPDGCTRL0_MODULE1_VALUE,  in config_mmdc()
126 		writel(MMDC_MPDGCTRL1_MODULE1_VALUE,  in config_mmdc()
131 	writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);  in config_mmdc()
132 	writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);  in config_mmdc()
133 	writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);  in config_mmdc()
134 	writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);  in config_mmdc()
135 	writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);  in config_mmdc()