Lines Matching refs:SIUL2_MSCRn
21 mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); in lpddr2_config_iomux()
22 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); in lpddr2_config_iomux()
24 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); in lpddr2_config_iomux()
25 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); in lpddr2_config_iomux()
27 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); in lpddr2_config_iomux()
28 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); in lpddr2_config_iomux()
31 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
34 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
37 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
40 writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
43 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); in lpddr2_config_iomux()
45 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); in lpddr2_config_iomux()
46 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); in lpddr2_config_iomux()
48 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); in lpddr2_config_iomux()
49 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); in lpddr2_config_iomux()
52 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
55 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
58 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
61 writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()