freescale/p2041rdb/ddr.c

4  * SPDX-License-Identifier:	GPL-2.0
33  *  wr_data_delay = 0-6
34  *  clk adjust = 0-8
35  *  cpo 2-0x1E (30)
61 	if (!pdimm->n_ranks)  in fsl_ddr_board_options()
71 	while (pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
72 		if (pbsp->n_ranks == pdimm->n_ranks) {  in fsl_ddr_board_options()
73 			if (ddr_freq <= pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
74 				popts->cpo_override = pbsp->cpo;  in fsl_ddr_board_options()
75 				popts->write_data_delay =  in fsl_ddr_board_options()
76 					pbsp->write_data_delay;  in fsl_ddr_board_options()
77 				popts->clk_adjust = pbsp->clk_adjust;  in fsl_ddr_board_options()
78 				popts->wrlvl_start = pbsp->wrlvl_start;  in fsl_ddr_board_options()
79 				popts->twot_en = pbsp->force_2t;  in fsl_ddr_board_options()
91 			ddr_freq, pbsp_highest->datarate_mhz_high);  in fsl_ddr_board_options()
92 		popts->cpo_override = pbsp_highest->cpo;  in fsl_ddr_board_options()
93 		popts->write_data_delay = pbsp_highest->write_data_delay;  in fsl_ddr_board_options()
94 		popts->clk_adjust = pbsp_highest->clk_adjust;  in fsl_ddr_board_options()
95 		popts->wrlvl_start = pbsp_highest->wrlvl_start;  in fsl_ddr_board_options()
96 		popts->twot_en = pbsp_highest->force_2t;  in fsl_ddr_board_options()
103 	 * Factors to consider for half-strength driver enable:  in fsl_ddr_board_options()
104 	 *	- number of DIMMs installed  in fsl_ddr_board_options()
106 	popts->half_strength_driver_enable = 0;  in fsl_ddr_board_options()
108 	popts->wrlvl_override = 1;  in fsl_ddr_board_options()
109 	popts->wrlvl_sample = 0xf;  in fsl_ddr_board_options()
112 	popts->rtt_override = 0;  in fsl_ddr_board_options()
115 	popts->zq_en = 1;  in fsl_ddr_board_options()
117 	/* DHC_EN =1, ODT = 60 Ohm */  in fsl_ddr_board_options()
118 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;  in fsl_ddr_board_options()
132 		return -ENXIO;  in dram_init()
139 	gd->ram_size = dram_size;  in dram_init()