2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
7  * SPDX-License-Identifier:	GPL-2.0+
38  * Note that we need to byte-swap the value before it's written to the AD
79 	temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;  in diu_set_pixel_clock()
80 	out_be32(&gur->clkdvdr, temp);			/* turn off clock */  in diu_set_pixel_clock()
81 	out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));  in diu_set_pixel_clock()
93 	 * Indirect mode requires both BR0 and BR1 to be set to "GPCM",  in platform_diu_init()
97 	 * In FCM mode, writes go to the NAND controller, which does not pass  in platform_diu_init()
99 	 * mode, since we don't care about what's behind the localbus any  in platform_diu_init()
133 	 * We know that the upper bits are 0 for 32-bit addressing, or 0xF for  in platform_diu_init()
134 	 * 36-bit addressing.  in platform_diu_init()
154 	temp = in_8(&pixis->brdcfg1);  in platform_diu_init()
164 		name = "Single-Link LVDS";  in platform_diu_init()
173 	out_8(&pixis->brdcfg1, temp);  in platform_diu_init()
176 	 * Enable PIXIS indirect access mode.  This is a hack that allows us to  in platform_diu_init()
180 	setbits_8(&pixis->csr, PX_CTL_ALTACC);  in platform_diu_init()
192 	clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);  in platform_diu_init()
193 	pmuxcr = in_be32(&gur->pmuxcr);  in platform_diu_init()
199  * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
217 	/* Switch the muxes only if they're currently set to DIU mode */  in set_mux_to_lbc()
218 	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=  in set_mux_to_lbc()
221 		 * In DIU mode, the PIXIS can only be accessed indirectly  in set_mux_to_lbc()
229 		/* Disable indirect PIXIS mode */  in set_mux_to_lbc()
233 		/* Set the chip mux to LBC mode, so that writes go to flash. */  in set_mux_to_lbc()
234 		out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |  in set_mux_to_lbc()
236 		in_be32(&gur->pmuxcr);  in set_mux_to_lbc()
251  * set_mux_to_diu - re-enable the DIU muxing
259 	/* Set BR0 and BR1 to GPCM mode */  in set_mux_to_diu()
265 	/* Enable indirect PIXIS mode */  in set_mux_to_diu()
266 	setbits_8(&pixis->csr, PX_CTL_ALTACC);  in set_mux_to_diu()
273 	/* Set the chip mux to DIU mode. */  in set_mux_to_diu()
274 	out_be32(&gur->pmuxcr, pmuxcr);  in set_mux_to_diu()
275 	in_be32(&gur->pmuxcr);  in set_mux_to_diu()
279  * pixis_read - board-specific function to read from the PIXIS
282  * use PIXIS indirect mode if necessary.
288 	/* Use indirect mode if the mux is currently set to DIU mode */  in pixis_read()
289 	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=  in pixis_read()
301  * pixis_write - board-specific function to write to the PIXIS
304  * use PIXIS indirect mode if necessary.
310 	/* Use indirect mode if the mux is currently set to DIU mode */  in pixis_write()
311 	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=  in pixis_write()
315 		/* Do a read-back to ensure the write completed */  in pixis_write()
328 	 * in indirect mode, so switch to direct mode first.  in pixis_bank_reset()
332 	out_8(&pixis->vctl, 0);  in pixis_bank_reset()
333 	out_8(&pixis->vctl, 1);  in pixis_bank_reset()
340 void flash_write8(u8 value, void *addr)  in flash_write8()  argument
344 	__raw_writeb(value, addr);  in flash_write8()
347 		 * To ensure the post-write is completed to eLBC, software must  in flash_write8()
349 		 * before changing the eLBC_DIU from NOR mode to DIU mode.  in flash_write8()
353 		__raw_readb(addr);  in flash_write8()
358 void flash_write16(u16 value, void *addr)  in flash_write16()  argument
362 	__raw_writew(value, addr);  in flash_write16()
365 		 * To ensure the post-write is completed to eLBC, software must  in flash_write16()
367 		 * before changing the eLBC_DIU from NOR mode to DIU mode.  in flash_write16()
371 		__raw_readb(addr);  in flash_write16()
376 void flash_write32(u32 value, void *addr)  in flash_write32()  argument
380 	__raw_writel(value, addr);  in flash_write32()
383 		 * To ensure the post-write is completed to eLBC, software must  in flash_write32()
385 		 * before changing the eLBC_DIU from NOR mode to DIU mode.  in flash_write32()
389 		__raw_readb(addr);  in flash_write32()
394 void flash_write64(u64 value, void *addr)  in flash_write64()  argument
397 	uint32_t *p = addr;  in flash_write64()
411 		 * To ensure the post-write is completed to eLBC, software must  in flash_write64()
413 		 * before changing the eLBC_DIU from NOR mode to DIU mode.  We  in flash_write64()
414 		 * read addr+4 because we just wrote to addr+4, so that's how we  in flash_write64()
419 		__raw_readb(addr + 4);  in flash_write64()
424 u8 flash_read8(void *addr)  in flash_read8()  argument
430 	ret = __raw_readb(addr);  in flash_read8()
437 u16 flash_read16(void *addr)  in flash_read16()  argument
443 	ret = __raw_readw(addr);  in flash_read16()
450 u32 flash_read32(void *addr)  in flash_read32()  argument
456 	ret = __raw_readl(addr);  in flash_read32()
463 u64 flash_read64(void *addr)  in flash_read64()  argument
470 	ret = *(volatile u64 *)addr;  in flash_read64()