Lines Matching +full:0 +full:x00000028

69 	return 0;  in dram_init()
159 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); in setup_fec()
161 ret = enable_fec_anatop_clock(0, ENET_125MHZ); in setup_fec()
169 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); in setup_fec()
172 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); in setup_fec()
180 return 0; in setup_fec()
197 .gp = IMX_GPIO_NR(1, 0),
217 if (ret < 0) in power_init_board()
226 return 0; in power_init_board()
230 #define USB_OTHERREGS_OFFSET 0x800
268 return 0; in board_ehci_hcd_init()
276 * Phy control debug reg 0 in board_phy_config()
278 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
279 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); in board_phy_config()
282 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in board_phy_config()
283 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in board_phy_config()
288 return 0; in board_phy_config()
306 return 0; in board_early_init_f()
310 {USDHC2_BASE_ADDR, 0, 4},
327 int ret = 0; in board_mmc_getcd()
356 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { in board_mmc_init()
358 case 0: in board_mmc_init()
361 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
389 return 0; in board_mmc_init()
397 if ((val & 0xc0) != 0x40) { in board_mmc_init()
402 port = (val >> 11) & 0x3; in board_mmc_init()
408 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
409 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
416 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
417 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
423 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); in board_mmc_init()
424 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; in board_mmc_init()
428 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
429 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
465 return 0; in board_qspi_init()
512 gpio_direction_output(IMX_GPIO_NR(3, 27) , 0); in setup_lcd()
519 return 0; in setup_lcd()
526 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; in board_init()
529 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); in board_init()
540 return 0; in board_init()
547 return 0; in checkboard()
556 .dram_dqm0 = 0x00000028,
557 .dram_dqm1 = 0x00000028,
558 .dram_dqm2 = 0x00000028,
559 .dram_dqm3 = 0x00000028,
560 .dram_ras = 0x00000020,
561 .dram_cas = 0x00000020,
562 .dram_odt0 = 0x00000020,
563 .dram_odt1 = 0x00000020,
564 .dram_sdba2 = 0x00000000,
565 .dram_sdcke0 = 0x00003000,
566 .dram_sdcke1 = 0x00003000,
567 .dram_sdclk_0 = 0x00000030,
568 .dram_sdqs0 = 0x00000028,
569 .dram_sdqs1 = 0x00000028,
570 .dram_sdqs2 = 0x00000028,
571 .dram_sdqs3 = 0x00000028,
572 .dram_reset = 0x00000020,
576 .grp_addds = 0x00000020,
577 .grp_ddrmode_ctl = 0x00020000,
578 .grp_ddrpke = 0x00000000,
579 .grp_ddrmode = 0x00020000,
580 .grp_b0ds = 0x00000028,
581 .grp_b1ds = 0x00000028,
582 .grp_ctlds = 0x00000020,
583 .grp_ddr_type = 0x000c0000,
584 .grp_b2ds = 0x00000028,
585 .grp_b3ds = 0x00000028,
589 .p0_mpwldectrl0 = 0x00290025,
590 .p0_mpwldectrl1 = 0x00220022,
591 .p0_mpdgctrl0 = 0x41480144,
592 .p0_mpdgctrl1 = 0x01340130,
593 .p0_mprddlctl = 0x3C3E4244,
594 .p0_mpwrdlctl = 0x34363638,
614 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
615 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
616 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
617 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
618 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
619 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
620 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
621 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
630 .cs1_mirror = 0, in spl_dram_init()
637 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
638 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
668 memset(__bss_start, 0, __bss_end - __bss_start); in board_init_f()
671 board_init_r(NULL, 0); in board_init_f()