Lines Matching full:r1
34 ldr r1, =DBG_CSCR_U_CONFIG
35 str r1, [r0, #0x00]
36 ldr r1, =DBG_CSCR_L_CONFIG
37 str r1, [r0, #0x04]
38 ldr r1, =DBG_CSCR_A_CONFIG
39 str r1, [r0, #0x08]
47 ldr r1, [r0, #CLKCTL_COSR]
48 bic r1, r1, #0x00000FF00
49 bic r1, r1, #0x0000000FF
52 orr r1, r1, r2
53 str r1, [r0, #CLKCTL_COSR]
58 check_soc_version r1, r2
59 cmp r1, #CHIP_REV_2_0
69 ldr r1, =CCM_PPLL_300_HZ
70 str r1, [r0, #CLKCTL_PPCTL]
72 ldr r1, =CCM_PDR0_CONFIG
73 bic r1, r1, #0x800000
74 str r1, [r0, #CLKCTL_PDR0]
76 ldr r1, [r0, #CLKCTL_CGR0]
77 orr r1, r1, #0x0C300000
78 str r1, [r0, #CLKCTL_CGR0]
80 ldr r1, [r0, #CLKCTL_CGR1]
81 orr r1, r1, #0x00000C00
82 orr r1, r1, #0x00000003
83 str r1, [r0, #CLKCTL_CGR1]
85 ldr r1, [r0, #CLKCTL_CGR2]
86 orr r1, r1, #0x00C00000
87 str r1, [r0, #CLKCTL_CGR2]
101 mov r1, #CSD0_BASE_ADDR
106 mov r1, #CSD1_BASE_ADDR
146 * r0: ESDCTL control base, r1: sdram slot base
165 cmp r1, #CSD1_BASE_ADDR
174 strb r3, [r1, r4]
179 cmp r1, #CSD1_BASE_ADDR
185 strb r3, [r1, r4]
187 strb r3, [r1, r4]
189 strb r3, [r1, r4]
191 strb r3, [r1, r4]
198 strb r3, [r1, r4]
201 cmp r1, #CSD1_BASE_ADDR
206 strb r3, [r1]
207 strb r3, [r1]
216 strb r3, [r1, r4]
218 streqb r3, [r1, r4]
221 strb r3, [r1, r4]
223 cmp r1, #CSD1_BASE_ADDR
234 str r3, [r1, #0x100]
235 ldr r4, [r1, #0x100]