Lines Matching +full:0 +full:x43f00000
36 ldr r0, =0x43F00000
37 ldr r1, =0x77777777
38 str r1, [r0, #0x00]
39 str r1, [r0, #0x04]
40 ldr r0, =0x53F00000
41 str r1, [r0, #0x00]
42 str r1, [r0, #0x04]
47 * (offset 0x20) access type
49 ldr r0, =0x43F00000
50 ldr r1, =0x0
51 str r1, [r0, #0x40]
52 str r1, [r0, #0x44]
53 str r1, [r0, #0x48]
54 str r1, [r0, #0x4C]
55 ldr r1, [r0, #0x50]
56 and r1, r1, #0x00FFFFFF
57 str r1, [r0, #0x50]
59 ldr r0, =0x53F00000
60 ldr r1, =0x0
61 str r1, [r0, #0x40]
62 str r1, [r0, #0x44]
63 str r1, [r0, #0x48]
64 str r1, [r0, #0x4C]
65 ldr r1, [r0, #0x50]
66 and r1, r1, #0x00FFFFFF
67 str r1, [r0, #0x50]
72 ldr r0, =0x43F04000
74 ldr r1, =0x00302154
75 str r1, [r0, #0x000] /* for S0 */
76 str r1, [r0, #0x100] /* for S1 */
77 str r1, [r0, #0x200] /* for S2 */
78 str r1, [r0, #0x300] /* for S3 */
79 str r1, [r0, #0x400] /* for S4 */
81 ldr r1, =0x10
82 str r1, [r0, #0x010] /* for S0 */
83 str r1, [r0, #0x110] /* for S1 */
84 str r1, [r0, #0x210] /* for S2 */
85 str r1, [r0, #0x310] /* for S3 */
86 str r1, [r0, #0x410] /* for S4 */
88 ldr r1, =0x0
89 str r1, [r0, #0x800] /* for M0 */
90 str r1, [r0, #0x900] /* for M1 */
91 str r1, [r0, #0xA00] /* for M2 */
92 str r1, [r0, #0xB00] /* for M3 */
93 str r1, [r0, #0xC00] /* for M4 */
94 str r1, [r0, #0xD00] /* for M5 */
100 ldr r1, =0xB8003000
103 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
104 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
105 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
106 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
107 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
108 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
109 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
110 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
112 * 0x00000040
114 ldr r0, =0x00000040
126 ldr r1, =0x43FAC200
127 ldr r0, [r1, #0x6C]
129 str r0, [r1, #0x6C]
132 ldr r0, [r1, #0x70]
134 str r0, [r1, #0x70]
137 ldr r0, [r1, #0x74]
139 str r0, [r1, #0x74]
142 ldr r0, [r1, #0x7C]
144 str r0, [r1, #0x7C]
147 ldr r0, [r1, #0x84]
149 str r0, [r1, #0x84]
151 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
152 ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
154 ldr r0, [r1, #0x88]
158 str r0, [r1, #0x88]
160 subs r2, r2, #0x1
167 ldr r1, =0x0000D843
168 str r1, [r0, #0x40]
169 ldr r1, =0x22252521
170 str r1, [r0, #0x44]
171 ldr r1, =0x22220A00
172 str r1, [r0, #0x48]
182 ldr r0, =0x40000015 /* start from AIPS 2GB region */
183 mcr p15, 0, r0, c15, c2, 4
199 REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
201 DELAY 0x40000
203 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
204 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
208 ldrh r1, [r1, #0x2]
210 ands r1, r1, #0x10
214 ldr r1, =0xFF871D58
216 str r1, [r0, #0x4]
220 str r1, [r0, #0x10]
223 ldr r1, =0x49FCFE7F
225 str r1, [r0, #0x8]
229 str r1, [r0, #0x14]
231 mov r1, #0x000002C0
232 add r1, r1, #0x00000006
234 str r1, [r0, #0x1c]
236 /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
237 …SI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_I…
239 /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
240 /* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
245 REG 0xB8001010, 0x00000004
246 REG 0xB8001004, 0x006ac73a
247 REG 0xB8001000, 0x92100000
248 REG 0x80000f00, 0x12344321
249 REG 0xB8001000, 0xa2100000
250 REG 0x80000000, 0x12344321
251 REG 0x80000000, 0x12344321
252 REG 0xB8001000, 0xb2100000
253 REG8 0x80000033, 0xda
254 REG8 0x81000000, 0xff
255 REG 0xB8001000, 0x82226080
256 REG 0x80000000, 0xDEADBEEF
257 REG 0xB8001010, 0x0000000c
262 .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
264 .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
266 .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
268 .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))