Lines Matching +full:dual +full:- +full:link
2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
23 volatile ccsr_gur_t *gur = &immap->im_gur; in diu_set_pixel_clock()
24 volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; in diu_set_pixel_clock()
48 temp = in_8(&pixis->brdcfg0); in platform_diu_init()
51 /* Dual link LVDS */ in platform_diu_init()
54 name = "Dual-Link LVDS"; in platform_diu_init()
56 /* Single link LVDS */ in platform_diu_init()
58 name = "Single-Link LVDS"; in platform_diu_init()
61 if (in_8(&pixis->ver) == 1) /* Board version */ in platform_diu_init()
68 out_8(&pixis->brdcfg0, temp); in platform_diu_init()