2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
4  * SPDX-License-Identifier:	GPL-2.0+
11 #include <asm/mmu.h>
59  * Fixed sdram init -- doesn't use serial presence detect.
65 	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;  in fixed_sdram()
68 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;  in fixed_sdram()
69 	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;  in fixed_sdram()
71 	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;  in fixed_sdram()
72 	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;  in fixed_sdram()
73 	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
74 	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;  in fixed_sdram()
75 	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;  in fixed_sdram()
76 	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;  in fixed_sdram()
77 	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;  in fixed_sdram()
78 	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;  in fixed_sdram()
79 	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;  in fixed_sdram()
80 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;  in fixed_sdram()
83 	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;  in fixed_sdram()
84 	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;  in fixed_sdram()
85 	ddr->err_sbe = CONFIG_SYS_DDR_SBE;  in fixed_sdram()
89 	udelay(500);  in fixed_sdram()
91 	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;  in fixed_sdram()
95 	debug("DDR - 1st controller: memory initializing\n");  in fixed_sdram()
100 	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {  in fixed_sdram()
105 	udelay(500);  in fixed_sdram()
124 		u8 uli_busno = hose->first_busno + 2;  in pci_init_board()
129 		 * Device 1d has the first on-board memory BAR.  in pci_init_board()
150 	 * Remap Boot flash + PROMJET region to caching-inhibited  in board_early_init_r()
154 	/* Flush d-cache and invalidate i-cache of any FLASH data */  in board_early_init_r()
158 	if (flash_esel == -1) {  in board_early_init_r()