6  * SPDX-License-Identifier:	GPL-2.0+
67 	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;  in dram_init()  local
70 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)  in dram_init()
71 		return -ENXIO;  in dram_init()
84 	gd->ram_size = msize * 1024 * 1024;  in dram_init()
91  *  fixed sdram init -- doesn't use serial presence detect.
95 	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;  in fixed_sdram()  local
99 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;  in fixed_sdram()
100 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);  in fixed_sdram()
102 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;  in fixed_sdram()
105 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;  in fixed_sdram()
108 	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;  in fixed_sdram()
109 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;  in fixed_sdram()
112 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;  in fixed_sdram()
113 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
114 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;  in fixed_sdram()
115 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;  in fixed_sdram()
116 	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;  in fixed_sdram()
117 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;  in fixed_sdram()
118 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;  in fixed_sdram()
119 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;  in fixed_sdram()
120 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;  in fixed_sdram()
124 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;  in fixed_sdram()
140 	u32 spridr = in_be32(&immr->sysconf.spridr);  in board_early_init_f()
172 	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;  in board_mmc_init()  local
182 	clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);  in board_mmc_init()
183 	clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);  in board_mmc_init()
190  * Miscellaneous late-boot configurations