5  * SPDX-License-Identifier:	GPL-2.0+
53 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;  in dram_init()  local
56 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)  in dram_init()
57 		return -ENXIO;  in dram_init()
59 	/* DDR SDRAM - Main SODIMM */  in dram_init()
60 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;  in dram_init()
78 	/* set total bus SDRAM size(bytes)  -- DDR */  in dram_init()
79 	gd->ram_size = msize;  in dram_init()
86  *  fixed sdram init -- doesn't use serial presence detect.
90 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;  in fixed_sdram()  local
95 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;  in fixed_sdram()
96 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);  in fixed_sdram()
102 	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;  in fixed_sdram()
103 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;  in fixed_sdram()
104 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;  in fixed_sdram()
105 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
106 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;  in fixed_sdram()
107 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;  in fixed_sdram()
108 	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;  in fixed_sdram()
109 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;  in fixed_sdram()
110 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;  in fixed_sdram()
111 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;  in fixed_sdram()
112 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;  in fixed_sdram()
113 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;  in fixed_sdram()
119 	im->ddr.csbnds[2].csbnds =  in fixed_sdram()
121 		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>  in fixed_sdram()
123 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;  in fixed_sdram()
126 	im->ddr.cs_config[0] = 0;  in fixed_sdram()
127 	im->ddr.cs_config[1] = 0;  in fixed_sdram()
128 	im->ddr.cs_config[3] = 0;  in fixed_sdram()
130 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
131 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;  in fixed_sdram()
133 	im->ddr.sdram_cfg =  in fixed_sdram()
140 	/* for 32-bit mode burst length is 8 */  in fixed_sdram()
141 	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);  in fixed_sdram()
143 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;  in fixed_sdram()
145 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;  in fixed_sdram()
150 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;  in fixed_sdram()
185 	volatile fsl_lbc_t *lbc = &immap->im_lbc;  in sdram_init()
193 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;  in sdram_init()
194 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;  in sdram_init()
195 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;  in sdram_init()
201 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */  in sdram_init()
203 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */  in sdram_init()
208 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */  in sdram_init()
236 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;  in sdram_init()
241 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */  in sdram_init()
266 	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];  in spi_cs_activate()
268 	iopd->dat &= ~SPI_CS_MASK;  in spi_cs_activate()
273 	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];  in spi_cs_deactivate()
275 	iopd->dat |=  SPI_CS_MASK;  in spi_cs_deactivate()