6  * SPDX-License-Identifier:	GPL-2.0+
23 #include "../common/pq-mds-pib.h"
36 	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
44 	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
55 	{3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
63 	{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
95 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;  in dram_init()  local
98 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)  in dram_init()
99 		return -ENXIO;  in dram_init()
101 	/* DDR SDRAM - Main SODIMM */  in dram_init()
102 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;  in dram_init()
106 	/* set total bus SDRAM size(bytes)  -- DDR */  in dram_init()
107 	gd->ram_size = msize * 1024 * 1024;  in dram_init()
113  *  fixed sdram init -- doesn't use serial presence detect.
117 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;  in fixed_sdram()  local
126 			return -1;  in fixed_sdram()
129 	im->sysconf.ddrlaw[0].ar =  in fixed_sdram()
130 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);  in fixed_sdram()
134 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;  in fixed_sdram()
135 	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;  in fixed_sdram()
136 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;  in fixed_sdram()
137 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;  in fixed_sdram()
138 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
139 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;  in fixed_sdram()
140 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;  in fixed_sdram()
141 	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;  in fixed_sdram()
142 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;  in fixed_sdram()
143 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;  in fixed_sdram()
144 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;  in fixed_sdram()
145 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;  in fixed_sdram()
149 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;  in fixed_sdram()