Lines Matching refs:EMI1_SLOT3
71 #define EMI1_SLOT3 2 macro
481 lane_to_slot_fsm1[0] = EMI1_SLOT3; in initialize_dpmac_to_slot()
482 lane_to_slot_fsm1[1] = EMI1_SLOT3; in initialize_dpmac_to_slot()
483 lane_to_slot_fsm1[2] = EMI1_SLOT3; in initialize_dpmac_to_slot()
491 lane_to_slot_fsm1[4] = EMI1_SLOT3; in initialize_dpmac_to_slot()
492 lane_to_slot_fsm1[5] = EMI1_SLOT3; in initialize_dpmac_to_slot()
493 lane_to_slot_fsm1[6] = EMI1_SLOT3; in initialize_dpmac_to_slot()
501 lane_to_slot_fsm1[0] = EMI1_SLOT3; in initialize_dpmac_to_slot()
502 lane_to_slot_fsm1[1] = EMI1_SLOT3; in initialize_dpmac_to_slot()
511 lane_to_slot_fsm1[4] = EMI1_SLOT3; in initialize_dpmac_to_slot()
512 lane_to_slot_fsm1[5] = EMI1_SLOT3; in initialize_dpmac_to_slot()
659 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3; in ls2080a_handle_phy_interface_sgmii()
660 bus = mii_dev_for_muxval(EMI1_SLOT3); in ls2080a_handle_phy_interface_sgmii()
879 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); in board_eth_init()