16 void fsl_ddr_board_options(memctl_options_t *popts,  in fsl_ddr_board_options()  argument
44 	if (popts->registered_dimm_en)  in fsl_ddr_board_options()
58 				popts->clk_adjust = pbsp->clk_adjust;  in fsl_ddr_board_options()
59 				popts->wrlvl_start = pbsp->wrlvl_start;  in fsl_ddr_board_options()
60 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
61 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
73 		popts->clk_adjust = pbsp_highest->clk_adjust;  in fsl_ddr_board_options()
74 		popts->wrlvl_start = pbsp_highest->wrlvl_start;  in fsl_ddr_board_options()
75 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
76 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
89 		popts->data_bus_width = 1;  in fsl_ddr_board_options()
90 		popts->otf_burst_chop_en = 0;  in fsl_ddr_board_options()
91 		popts->burst_length = DDR_BL8;  in fsl_ddr_board_options()
92 		popts->bstopre = 0;	/* enable auto precharge */  in fsl_ddr_board_options()
123 	popts->half_strength_driver_enable = 0;  in fsl_ddr_board_options()
127 	popts->wrlvl_override = 1;  in fsl_ddr_board_options()
128 	popts->wrlvl_sample = 0x0;	/* 32 clocks */  in fsl_ddr_board_options()
133 	popts->rtt_override = 0;  in fsl_ddr_board_options()
136 	popts->zq_en = 1;  in fsl_ddr_board_options()
141 			popts->ddr_cdr1 = DDR_CDR1_DHC_EN |  in fsl_ddr_board_options()
143 			popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);  in fsl_ddr_board_options()
144 			popts->twot_en = 1; /* enable 2T timing */  in fsl_ddr_board_options()
146 			popts->ddr_cdr1 = DDR_CDR1_DHC_EN |  in fsl_ddr_board_options()
148 			popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |  in fsl_ddr_board_options()
152 		popts->ddr_cdr1 = DDR_CDR1_DHC_EN |  in fsl_ddr_board_options()
154 		popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |  in fsl_ddr_board_options()