Lines Matching refs:vid
244 u8 vid; in set_voltage_to_IR() local
251 vid = DIV_ROUND_UP(vdd - 265, 5); in set_voltage_to_IR()
253 vid = DIV_ROUND_UP(vdd - 245, 5); in set_voltage_to_IR()
257 1, (void *)&vid, sizeof(vid)); in set_voltage_to_IR()
293 u8 vid, buf; in adjust_vdd() local
333 u8 vid; in adjust_vdd() member
370 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
372 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
373 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
376 vdd_target = vdd[vid]; in adjust_vdd()
457 u8 vid, buf; in adjust_vdd() local
491 u8 vid; in adjust_vdd() member
546 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
548 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
549 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
553 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
555 if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
556 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
560 vdd_target = vdd[vid]; in adjust_vdd()