13 struct qixis {  struct
14 	u8 id;      /* ID value uniquely identifying each QDS board type */
15 	u8 arch;    /* Board version information */
16 	u8 scver;   /* QIXIS Version Register */
17 	u8 model;   /* Information of software programming model version */
18 	u8 tagdata;
19 	u8 ctl_sys;
20 	u8 aux;         /* Auxiliary Register,0x06 */
21 	u8 clk_spd;
22 	u8 stat_dut;
23 	u8 stat_sys;
24 	u8 stat_alrm;
25 	u8 present;
26 	u8 present2;    /* Presence Status Register 2,0x0c */
27 	u8 rcw_ctl;
28 	u8 ctl_led;
29 	u8 i2cblk;
30 	u8 rcfg_ctl;    /* Reconfig Control Register,0x10 */
31 	u8 rcfg_st;
32 	u8 dcm_ad;
33 	u8 dcm_da;
34 	u8 dcmd;
35 	u8 dmsg;
36 	u8 gdc;
37 	u8 gdd;         /* DCM Debug Data Register,0x17 */
38 	u8 dmack;
39 	u8 res1[6];
40 	u8 watch;       /* Watchdog Register,0x1F */
41 	u8 pwr_ctl[2];  /* Power Control Register,0x20 */
42 	u8 res2[2];
43 	u8 pwr_stat[4]; /* Power Status Register,0x24 */
44 	u8 res3[8];
45 	u8 clk_spd2[2];  /* SYSCLK clock Speed Register,0x30 */
46 	u8 res4[2];
47 	u8 sclk[3];  /* Clock Configuration Registers,0x34 */
48 	u8 res5;
49 	u8 dclk[3];
50 	u8 res6;
51 	u8 clk_dspd[3];
52 	u8 res7;
53 	u8 rst_ctl;     /* Reset Control Register,0x40 */
54 	u8 rst_stat;    /* Reset Status Register */
55 	u8 rst_rsn;     /* Reset Reason Register */
56 	u8 rst_frc[2];  /* Reset Force Registers,0x43 */
57 	u8 res8[11];
58 	u8 brdcfg[16];  /* Board Configuration Register,0x50 */
59 	u8 dutcfg[16];
60 	u8 rcw_ad[2];   /* RCW SRAM Address Registers,0x70 */
61 	u8 rcw_data;
62 	u8 res9[5];
63 	u8 post_ctl;
64 	u8 post_stat;
65 	u8 post_dat[2];
66 	u8 pi_d[4];
67 	u8 gpio_io[4];
68 	u8 gpio_dir[4];
92 u8 qixis_read(unsigned int reg);  argument
104 #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))  argument