65 		debug("Only one refclk at 122.88MHz is not supported."  in set_serdes_refclk()
66 			" Please set both refclk1 & refclk2 to 122.88MHz"  in set_serdes_refclk()
67 			" or both not to 122.88MHz.\n");  in set_serdes_refclk()
74 		debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"  in set_serdes_refclk()
75 			" or 156.25MHz.\n");  in set_serdes_refclk()
82 		debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"  in set_serdes_refclk()
83 			" or 156.25MHz.\n");  in set_serdes_refclk()
93 	 * Refclk1 = 122.88MHz  Refclk2 = 122.88MHz  in set_serdes_refclk()
118 	 * Refclk1 = 100MHz  Refclk2 = 125MHz  in set_serdes_refclk()
126 	 * Refclk1 = 125MHz  Refclk2 = 125MHz  in set_serdes_refclk()
135 	 * Refclk1 = 125MHz  Refclk2 = 100MHz  in set_serdes_refclk()
143 	 * Refclk1 = 156.25MHz  Refclk2 = 156.25MHz  in set_serdes_refclk()
154 	 * Refclk1 = 100MHz  Refclk2 = 156.25MHz  in set_serdes_refclk()
165 	 * Refclk1 = 125MHz  Refclk2 = 156.25MHz  in set_serdes_refclk()
176 	 * Refclk1 = 156.25MHz  Refclk2 = 100MHz  in set_serdes_refclk()
187 	 * Refclk1 = 156.25MHz  Refclk2 = 125MHz  in set_serdes_refclk()