47  * the result will be retuned with component RDW, VDW, OD, TTL,
53 	unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;  in ics307_sysclk_calculator()  local
62 			/* Calculate the VDW */  in ics307_sysclk_calculator()
63 			vdw = out_freq * 1000 * od * rdw / (input_freq * 2);  in ics307_sysclk_calculator()
64 			if (vdw > MAX_VDW)  in ics307_sysclk_calculator()
65 				vdw = MAX_VDW;  in ics307_sysclk_calculator()
66 			if (vdw < MIN_VDW)  in ics307_sysclk_calculator()
69 			tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);  in ics307_sysclk_calculator()
79 				s_vdw = vdw;  in ics307_sysclk_calculator()
92 	debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,  in ics307_sysclk_calculator()
104 	unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);  in ics307_clk_freq()  local
110 	 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)  in ics307_clk_freq()
117 	 * V8:V0 = VCO Divider Word (VDW)  in ics307_clk_freq()
125 	freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);  in ics307_clk_freq()