39 /* decode S[0-2] to Output Divider (OD) */
47  * the result will be retuned with component RDW, VDW, OD, TTL,
53 	unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;  in ics307_sysclk_calculator()  local
58 		od = ics307_s_to_od[odp];  in ics307_sysclk_calculator()
59 		if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)  in ics307_sysclk_calculator()
63 			vdw = out_freq * 1000 * od * rdw / (input_freq * 2);  in ics307_sysclk_calculator()
69 			tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);  in ics307_sysclk_calculator()
92 	debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,  in ics307_sysclk_calculator()
106 	unsigned long od = ics307_s_to_od[cw0 & 0x7];  in ics307_clk_freq()  local
110 	 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)  in ics307_clk_freq()
118 	 * S2:S0 = Output Divider Select (OD)  in ics307_clk_freq()
125 	freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);  in ics307_clk_freq()