freescale/b4860qds/tlb.c

11 	/* TLB 0 - for temp stack in cache */
12 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
14 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
15 		      0, 0, BOOKE_PAGESZ_4K, 0),
16 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 		      0, 0, BOOKE_PAGESZ_4K, 0),
20 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 		      0, 0, BOOKE_PAGESZ_4K, 0),
24 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
26 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
27 		      0, 0, BOOKE_PAGESZ_4K, 0),
34 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
38 			0, 0, BOOKE_PAGESZ_1M, 1),
42 	 * space is at 0xfff00000, it covered the 0xfffff000.
47 		      0, 0, BOOKE_PAGESZ_1M, 1),
49 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
51 		      0, 0, BOOKE_PAGESZ_4K, 1),
57 		      0, 1, BOOKE_PAGESZ_16M, 1),
63 		      0, 2, BOOKE_PAGESZ_256M, 1),
69 		      0, 3, BOOKE_PAGESZ_256M, 1),
71 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
72 		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
74 		      0, 4, BOOKE_PAGESZ_256M, 1),
79 		      0, 5, BOOKE_PAGESZ_64K, 1),
84 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
85 		      0, 6, BOOKE_PAGESZ_16M, 1),
86 	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
87 		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
89 		      0, 7, BOOKE_PAGESZ_16M, 1),
93 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
94 		      0, 8, BOOKE_PAGESZ_16M, 1),
95 	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
96 		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
98 		      0, 9, BOOKE_PAGESZ_16M, 1),
104 		      0, 10, BOOKE_PAGESZ_32M, 1),
112 			0, 11, BOOKE_PAGESZ_64K, 1),
116 		      0, 12, BOOKE_PAGESZ_4K, 1),
128 		      0, 13, BOOKE_PAGESZ_256M, 1),
134 		      0, 16, BOOKE_PAGESZ_256M, 1),
138 	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
144 		      0, 17, BOOKE_PAGESZ_1M, 1),
150 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
151 		      0, 17, BOOKE_PAGESZ_2G, 1)