Lines Matching full:lanes
41 * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
74 * Lanes: A,B,C,D: SGMII in initialize_lane_to_slot()
75 * Lanes: E,F: Aur in initialize_lane_to_slot()
76 * Lanes: G,H: SRIO in initialize_lane_to_slot()
82 * Lanes: A,B: SGMII in initialize_lane_to_slot()
83 * Lanes: C,D: SRIO2 in initialize_lane_to_slot()
84 * Lanes: E,F,G,H: XAUI2 in initialize_lane_to_slot()
90 * Lanes: A,B,C,D: SGMII in initialize_lane_to_slot()
91 * Lanes: E,F,G,H: XAUI2 in initialize_lane_to_slot()
97 * Lanes: A,B,C,D: XAUI2 in initialize_lane_to_slot()
98 * Lanes: E,F,G,H: XAUI2 in initialize_lane_to_slot()
104 * Lanes: A,B: PCI in initialize_lane_to_slot()
105 * Lanes: C,D: SGMII in initialize_lane_to_slot()
106 * Lanes: E,F,G,H: XAUI2 in initialize_lane_to_slot()
112 * Lanes: A,B,C,D: PCI in initialize_lane_to_slot()
113 * Lanes: E,F,G,H: XAUI2 in initialize_lane_to_slot()
122 * Lanes: A,B,C,D: PCI in initialize_lane_to_slot()
123 * Lanes: E,F: SGMII 3&4 in initialize_lane_to_slot()
124 * Lanes: G,H: XFI in initialize_lane_to_slot()
130 * Lanes: A,B: SGMII in initialize_lane_to_slot()
131 * Lanes: C,D: SRIO2 in initialize_lane_to_slot()
132 * Lanes: E,F,G,H: XAUI2 in initialize_lane_to_slot()