Lines Matching full:serdes
15 * one Fman device on B4860. The SERDES configuration is used to determine
19 * is done at boot time by reading SERDES protocol from RCW.
41 * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
73 * SERDES: 2 in initialize_lane_to_slot()
81 * SERDES: 2 in initialize_lane_to_slot()
89 * SERDES: 2 in initialize_lane_to_slot()
96 * SERDES: 2 in initialize_lane_to_slot()
103 * SERDES: 2 in initialize_lane_to_slot()
111 * SERDES: 2 in initialize_lane_to_slot()
121 * SERDES: 2 in initialize_lane_to_slot()
129 * SERDES: 2 in initialize_lane_to_slot()
207 /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ in board_eth_init()
219 /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ in board_eth_init()
223 /* Fixing Serdes clock by programming FPGA register */ in board_eth_init()