66 	 * Display the actual SERDES reference clocks as configured by the  in checkboard()
69 	 * values that the SERDES expects (or vice versa).  For now, however,  in checkboard()
73 	puts("SERDES Reference Clocks: ");  in checkboard()
365 			 * SERDES: 1  in configure_vsc3316_3308()
414 			 * SERDES: 1  in configure_vsc3316_3308()
445 			 * SERDES: 1  in configure_vsc3316_3308()
601 	/* Steps For SerDes PLLs reset and reconfiguration  in calibrate_pll()
792 	/* To prevent generation of reset request from SerDes  in config_serdes1_refclks()
794 	 * SerDes reset event cannot cause a reset request  in config_serdes1_refclks()
830 		debug("Configuring idt8t49n222a for CPRI SerDes clks:"  in config_serdes1_refclks()
871 		/* Steps For SerDes PLLs reset and reconfiguration after  in config_serdes1_refclks()
872 		 * changing SerDes's refclks  in config_serdes1_refclks()
898 	 * SerDes reset event can cause a reset request  in config_serdes1_refclks()
922 	/* To prevent generation of reset request from SerDes  in config_serdes2_refclks()
924 	 * SerDes reset event cannot cause a reset request  in config_serdes2_refclks()
957 		/* Steps For SerDes PLLs reset and reconfiguration after  in config_serdes2_refclks()
958 		 * changing SerDes's refclks  in config_serdes2_refclks()
983 	 * SerDes reset event can cause a reset request  in config_serdes2_refclks()
1053 		printf("SerDes disable, Refclks couldn't change.\n");  in board_early_init_r()
1059 	/* Rechecking the SerDes locks after all SerDes configurations  in board_early_init_r()
1060 	 * are done, As SerDes PLLs may not lock reliably at 5 G VCO  in board_early_init_r()
1062 	 * Following sequence ensure the proper locking of SerDes PLLs.  in board_early_init_r()
1066 			printf("SerDes plls still not locked properly.\n");  in board_early_init_r()
1068 			printf("SerDes plls have been locked well.\n");  in board_early_init_r()
1183 			printf("Warning: SERDES bank %u expects reference clock"  in misc_init_r()