engicam/common/spl.c

49 	return 0;  in spl_start_uboot()
56  *   0x30 == 40 Ohm
57  *   0x28 == 48 Ohm
59 #define IMX6DQ_DRIVE_STRENGTH		0x30
60 #define IMX6SDL_DRIVE_STRENGTH		0x28
87 	.dram_sdba2 = 0x00000000,
103 	.grp_ddrmode_ctl = 0x00020000,
104 	.grp_ddrpke = 0x00000000,
105 	.grp_ddrmode = 0x00020000,
107 	.grp_ddr_type = 0x000c0000,
119 	.dram_sdba2 = 0x00000000,
142 	.grp_ddr_type = 0x000c0000,
143 	.grp_ddrmode_ctl = 0x00020000,
144 	.grp_ddrpke = 0x00000000,
147 	.grp_ddrmode = 0x00020000,
170 	.SRT = 0,
174 	.p0_mpwldectrl0 = 0x000E0009,
175 	.p0_mpwldectrl1 = 0x0018000E,
176 	.p1_mpwldectrl0 = 0x00000007,
177 	.p1_mpwldectrl1 = 0x00000000,
178 	.p0_mpdgctrl0 = 0x43280334,
179 	.p0_mpdgctrl1 = 0x031C0314,
180 	.p1_mpdgctrl0 = 0x4318031C,
181 	.p1_mpdgctrl1 = 0x030C0258,
182 	.p0_mprddlctl = 0x3E343A40,
183 	.p1_mprddlctl = 0x383C3844,
184 	.p0_mpwrdlctl = 0x40404440,
185 	.p1_mpwrdlctl = 0x4C3E4446,
192 	.cs1_mirror	= 0,
200 	.walat		= 0,
202 	.rst_to_cke	= 0x23,
203 	.sde_to_rst	= 0x10,
207 	.p0_mpwldectrl0 = 0x001F0024,
208 	.p0_mpwldectrl1 = 0x00110018,
209 	.p1_mpwldectrl0 = 0x001F0024,
210 	.p1_mpwldectrl1 = 0x00110018,
211 	.p0_mpdgctrl0 = 0x4230022C,
212 	.p0_mpdgctrl1 = 0x02180220,
213 	.p1_mpdgctrl0 = 0x42440248,
214 	.p1_mpdgctrl1 = 0x02300238,
215 	.p0_mprddlctl = 0x44444A48,
216 	.p1_mprddlctl = 0x46484A42,
217 	.p0_mpwrdlctl = 0x38383234,
218 	.p1_mpwrdlctl = 0x3C34362E,
224 	.cs1_mirror	= 0,
232 	.walat		= 0,
234 	.rst_to_cke	= 0x23,
235 	.sde_to_rst	= 0x10,
241 	.cs1_mirror	= 0,
249 	.walat		= 0,
251 	.rst_to_cke	= 0x23,
252 	.sde_to_rst	= 0x10,
258 	.grp_addds = 0x00000030,
259 	.grp_ddrmode_ctl = 0x00020000,
260 	.grp_b0ds = 0x00000030,
261 	.grp_ctlds = 0x00000030,
262 	.grp_b1ds = 0x00000030,
263 	.grp_ddrpke = 0x00000000,
264 	.grp_ddrmode = 0x00020000,
265 	.grp_ddr_type = 0x000c0000,
269 	.dram_dqm0 = 0x00000030,
270 	.dram_dqm1 = 0x00000030,
271 	.dram_ras = 0x00000030,
272 	.dram_cas = 0x00000030,
273 	.dram_odt0 = 0x00000030,
274 	.dram_odt1 = 0x00000030,
275 	.dram_sdba2 = 0x00000000,
276 	.dram_sdclk_0 = 0x00000008,
277 	.dram_sdqs0 = 0x00000038,
278 	.dram_sdqs1 = 0x00000030,
279 	.dram_reset = 0x00000030,
283 	.p0_mpwldectrl0 = 0x00070007,
284 	.p0_mpdgctrl0 = 0x41490145,
285 	.p0_mprddlctl = 0x40404546,
286 	.p0_mpwrdlctl = 0x4040524D,
290 	.dsize = 0,
293 	.cs1_mirror = 0,
300 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
301 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
328 	writel(0x00003F3F, &ccm->CCGR0);  in ccgr_init()
329 	writel(0x0030FC00, &ccm->CCGR1);  in ccgr_init()
330 	writel(0x000FC000, &ccm->CCGR2);  in ccgr_init()
331 	writel(0x3F300000, &ccm->CCGR3);  in ccgr_init()
332 	writel(0xFF00F300, &ccm->CCGR4);  in ccgr_init()
333 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
334 	writel(0x000003CC, &ccm->CCGR6);  in ccgr_init()
336 	writel(0x00c03f3f, &ccm->CCGR0);  in ccgr_init()
337 	writel(0xfcffff00, &ccm->CCGR1);  in ccgr_init()
338 	writel(0x0cffffcc, &ccm->CCGR2);  in ccgr_init()
339 	writel(0x3f3c3030, &ccm->CCGR3);  in ccgr_init()
340 	writel(0xff00fffc, &ccm->CCGR4);  in ccgr_init()
341 	writel(0x033f30ff, &ccm->CCGR5);  in ccgr_init()
342 	writel(0x00c00fff, &ccm->CCGR6);  in ccgr_init()
389 	memset(__bss_start, 0, __bss_end - __bss_start);  in board_init_f()
392 	board_init_r(NULL, 0);  in board_init_f()