Lines Matching refs:ODT
107 # bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
109 # bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
128 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
132 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
133 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
136 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
139 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
140 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
162 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
170 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
171 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
172 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
175 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
176 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
177 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
178 # bit9-8: 0, Internal ODT assertion is controlled by fiels
179 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
180 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
181 # bit14: 1, M_STARTBURST_IN ODT enabled
182 # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
183 # bit20-16: 0, Pad N channel driving strength for ODT
184 # bit25-21: 0, Pad P channel driving strength for ODT