Lines Matching full:assertion

130 # bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
131 # bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
132 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
133 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
137 # bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
138 # bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
139 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
140 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
171 # bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
172 # bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
178 # bit9-8:   0, Internal ODT assertion is controlled by fiels