compulab/cm_t43/spl.c

32 	.emif_sdram_config_ext	= 0x0143,
37 	.sdram_config			= 0x638413B2,
38 	.ref_ctrl			= 0x00000C30,
39 	.sdram_tim1			= 0xEAAAD4DB,
40 	.sdram_tim2			= 0x266B7FDA,
41 	.sdram_tim3			= 0x107F8678,
42 	.read_idle_ctrl			= 0x00050000,
43 	.zq_config			= 0x50074BE4,
44 	.temp_alert_config		= 0x0,
45 	.emif_ddr_phy_ctlr_1		= 0x0E004008,
46 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
47 	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
48 	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
49 	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
50 	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
51 	.emif_rd_wr_exec_thresh		= 0x80000405,
52 	.emif_prio_class_serv_map	= 0x80000001,
53 	.emif_connect_id_serv_1_map	= 0x80000094,
54 	.emif_connect_id_serv_2_map	= 0x00000000,
55 	.emif_cos_config		= 0x000FFFFF
59 	0x00000000,
60 	0x00000044,
61 	0x00000044,
62 	0x00000046,
63 	0x00000046,
64 	0x00000000,
65 	0x00000059,
66 	0x00000077,
67 	0x00000093,
68 	0x000000A8,
69 	0x00000000,
70 	0x00000019,
71 	0x00000037,
72 	0x00000053,
73 	0x00000068,
74 	0x00000000,
75 	0x0,
76 	0x0,
77 	0x40000000,
78 	0x08102040
122 	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);  in sdram_init()
123 	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);  in sdram_init()
124 	if (ram_size == 0x80000000 ||  in sdram_init()
125 	    ram_size == 0x40000000 ||  in sdram_init()
126 	    ram_size == 0x20000000)  in sdram_init()
129 	ddr3_emif_regs.sdram_config = 0x638453B2;  in sdram_init()
130 	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);  in sdram_init()
131 	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);  in sdram_init()
132 	if (ram_size == 0x08000000)  in sdram_init()