54 	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
55 	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7));  in set_muxconf_regs()
58 	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
59 	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
60 	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
61 	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
62 	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
63 	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
64 	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
65 	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
66 	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
67 	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
84 	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
89 	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | DIS  | M4));/*GPIO_54*/  in set_muxconf_regs()
91 	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | DIS  | M4));/*GPIO_58*/  in set_muxconf_regs()
95 	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
96 	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
97 	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
98 	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0));  in set_muxconf_regs()
100 	MUX_VAL(CP(GPMC_NBE1),		(IDIS | PTU | EN  | M4)); /*GPIO_61*/  in set_muxconf_regs()
108 	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
112 	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTU | EN  | M4)); /*GPIO_164*/  in set_muxconf_regs()
132 	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
133 	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
134 	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
135 	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
136 	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
137 	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
138 	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
139 	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
140 	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
141 	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
142 	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
143 	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
144 	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
145 	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
146 	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
147 	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
148 	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
149 	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
150 	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
151 	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
152 	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
153 	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
154 	MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
155 	MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
156 	MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
157 	MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
158 	MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
159 	MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
168 	MUX_VAL(CP(CCDC_WEN),		(IDIS | PTU | EN  | M4)); /*GPIO_98*/  in set_muxconf_regs()
170 	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)); /*GPIO_152*/  in set_muxconf_regs()
179 	MUX_VAL(CP(RMII_TXD0),		(IDIS | M0));  in set_muxconf_regs()
180 	MUX_VAL(CP(RMII_TXD1),		(IDIS | M0));  in set_muxconf_regs()
181 	MUX_VAL(CP(RMII_TXEN),		(IDIS | M0));  in set_muxconf_regs()
185 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*GPIO_186*/  in set_muxconf_regs()
193 	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)); /*GPIO_157*/  in set_muxconf_regs()
213 	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/  in set_muxconf_regs()
214 	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/  in set_muxconf_regs()
226 	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/  in set_muxconf_regs()
227 	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/  in set_muxconf_regs()