17 	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
18 	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
19 	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
20 	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
21 	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
22 	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
23 	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
24 	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
25 	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
26 	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
27 	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
28 	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
29 	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
30 	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
31 	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
32 	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
33 	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
34 	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
35 	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
36 	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
37 	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
38 	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
39 	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
40 	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
41 	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
42 	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
43 	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
44 	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
45 	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
46 	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
47 	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
48 	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
49 	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
50 	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
51 	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
52 	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
53 	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
55 	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7));  in set_muxconf_regs()
89 	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | DIS  | M4));/*GPIO_54*/  in set_muxconf_regs()
91 	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | DIS  | M4));/*GPIO_58*/  in set_muxconf_regs()
95 	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
96 	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
97 	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
101 	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
107 	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
108 	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
125 	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
126 	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
127 	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
128 	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
129 	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS  | M0));  in set_muxconf_regs()
132 	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
133 	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
134 	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
135 	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
136 	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
137 	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
138 	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
139 	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
140 	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
141 	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
142 	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
143 	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
144 	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
145 	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
146 	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
147 	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
148 	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
149 	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
150 	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
151 	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
152 	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
153 	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0));  in set_muxconf_regs()
154 	MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
155 	MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
156 	MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
157 	MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
158 	MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
159 	MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0));  in set_muxconf_regs()
170 	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)); /*GPIO_152*/  in set_muxconf_regs()
175 	MUX_VAL(CP(RMII_RXD0),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
176 	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
177 	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
178 	MUX_VAL(CP(RMII_RXER),		(IEN  | PTD | DIS | M0));  in set_muxconf_regs()
182 	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTU | DIS | M0));  in set_muxconf_regs()
185 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*GPIO_186*/  in set_muxconf_regs()
188 	MUX_VAL(CP(MCBSP1_CLKR),	(IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/  in set_muxconf_regs()
189 	MUX_VAL(CP(MCBSP1_DX),		(IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/  in set_muxconf_regs()
190 	MUX_VAL(CP(MCBSP1_DR),		(IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/  in set_muxconf_regs()
193 	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)); /*GPIO_157*/  in set_muxconf_regs()
198 	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTU | DIS | M4)); /*GPIO_162*/  in set_muxconf_regs()
213 	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/  in set_muxconf_regs()
214 	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/  in set_muxconf_regs()
226 	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/  in set_muxconf_regs()
227 	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/  in set_muxconf_regs()
230 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTU | DIS | M4)); /*GPIO_2*/  in set_muxconf_regs()
231 	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTU | DIS | M4)); /*GPIO_3*/  in set_muxconf_regs()
232 	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTU | DIS | M4)); /*GPIO_4*/  in set_muxconf_regs()
233 	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTU | DIS | M4)); /*GPIO_5*/  in set_muxconf_regs()
234 	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTU | DIS | M4)); /*GPIO_6*/  in set_muxconf_regs()
235 	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTU | DIS | M4)); /*GPIO_7*/  in set_muxconf_regs()