cloudengines/pogo_e02/kwbimage.cfg

8 # Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
10 # SPDX-License-Identifier:	GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
24 # Configure RGMII-0 interface pad voltage to 1.8V
29 # bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
30 # bit23-14: zero
31 # bit24: 1= enable exit self refresh mode on DDR access
33 # bit29-26: zero
34 # bit31-30: 01
38 # bit 5:    0=clk is driven during self refresh, we don't care for APX
40 # bit14:    0=input buffer always powered up
42 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
44 # bit30-28: 3 required
48 # bit3-0:   TRAS lsbs
49 # bit7-4:   TRCD
50 # bit11- 8: TRP
51 # bit15-12: TWR
52 # bit19-16: TWTR
54 # bit23-21: 0x0
55 # bit27-24: TRRD
56 # bit31-28: TRTP
59 # bit6-0:   TRFC
60 # bit8-7:   TR2R
61 # bit10-9:  TR2W
62 # bit12-11: TW2W
63 # bit31-13: zero required
66 # bit1-0:   00, Cs0width=x8
67 # bit3-2:   11, Cs0size=1Gb
68 # bit5-4:   00, Cs1width=x8
69 # bit7-6:   11, Cs1size=1Gb
70 # bit9-8:   00, Cs2width=nonexistent
71 # bit11-10: 00, Cs2size =nonexistent
72 # bit13-12: 00, Cs3width=nonexistent
73 # bit15-14: 00, Cs3size =nonexistent
78 # bit31-20: 0 required
82 # bit31-1: 0 required
85 # bit3-0:   0x0, DDR cmd
86 # bit31-4:  0 required
89 # bit2-0:   2, BurstLen=2 required
91 # bit6-4:   4, CL=5
94 # bit11-9:  6, auto-precharge write recovery ????????????
96 # bit31-13: 0 required
102 # bit5-3:  000, required
104 # bit9-7:  000, required
108 # bit31-13: 0 required
111 # bit2-0:  111, required
113 # bit6-4:  111, required
119 # bit15-12: 1111 required
120 # bit31-16: 0    required
129 # bit3-2:  00, CS0 hit selected
130 # bit23-4: ones, required
131 # bit31-24: 0x0F, Size (i.e. 256MB)
140 # bit3-0:  2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
141 # bit7-4:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
142 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
143 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
146 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
147 # bit3-2:  01, ODT1 active NEVER!
148 # bit31-4: zero, required