Lines Matching +full:0 +full:x021b0000

38 DATA 4 0x020c4068 0xffffffff
39 DATA 4 0x020c406c 0xffffffff
40 DATA 4 0x020c4070 0xffffffff
41 DATA 4 0x020c4074 0xffffffff
42 DATA 4 0x020c4078 0xffffffff
43 DATA 4 0x020c407c 0xffffffff
44 DATA 4 0x020c4080 0xffffffff
45 DATA 4 0x020c4084 0xffffffff
48 DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
49 DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
52 DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
55 DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
56 DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
57 DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
58 DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
59 DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
62 DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
63 DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
64 DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
67 DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
68 DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
69 DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
72 DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
73 DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
74 DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
75 DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
76 DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
91 DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
97 DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
104 DATA 4 0x021b080c 0x00000000
107 DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
110 DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
113 DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
117  * reset value is 0)
119 DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
120 DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
121 DATA 4 0x021b082c 0xF3333333
122 DATA 4 0x021b0830 0xF3333333
124 DATA 4 0x021b08c0 0x00921012
127 DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
130 DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
136 DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
137 DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
138 DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
139 DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
140 DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
150 DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
152 DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
155 DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
156 DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
157 DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
158 DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
161 DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
162 DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
163 DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
164 DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
165 DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
168 DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
169 DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
170 DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
171 DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
174 DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially