Lines Matching refs:ODT

116 # bit2:     1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
118 # bit6:     0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
138 # DDR2 ODT Read Timing (default values)
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # DDR2 ODT Write Timing (default values)
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
179 # DDR ODT Control (Low)
188 # DDR ODT Control (High)
190 # bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
191 # bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
194 # CPU ODT Control
196 # bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
197 # bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
198 # bit9-8:   0, Internal ODT assertion is controlled by fiels
199 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
200 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
201 # bit14:    1, M_STARTBURST_IN ODT enabled
202 # bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
203 # bit20-16: 0, Pad N channel driving strength for ODT
204 # bit25-21: 0, Pad P channel driving strength for ODT