buffalo/lsxl/kwbimage-lsxhl.cfg

5 # SPDX-License-Identifier:	GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
17 # Configure RGMII-0/1 interface pad voltage to 1.8V
30 # bit13-0:  0x618, 1560 DDR2 clks refresh rate
31 # bit23-14: 0 required
34 # bit29-26: 0 required
35 # bit31-30: 0b01 required
39 # bit3-0:   0 required
43 # bit11-7:  0 required
47 # bit17-15: 0 required
50 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
51 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
52 # bit30-28: 3 required
57 # bit3-0:   0x1, 18 cycle tRAS (tRAS[3-0])
58 # bit7-4:   4, 5 cycle tRCD
59 # bit11-8:  4, 5 cyle tRP
60 # bit15-12: 5, 6 cyle tWR
61 # bit19-16: 2, 3 cyle tWTR
63 # bit23-21: 0 required
64 # bit27-24: 2, 3 cycle tRRD
65 # bit31-28: 2, 3 cyle tRTP
69 # bit6-0:   0x32, 50 cycle tRFC
70 # bit8-7:   0, 1 cycle tR2R
71 # bit10-9:  0, 1 cyle tR2W
72 # bit12-11: 1, 2 cylce tW2W
73 # bit31-13: 0 required
77 # bit1-0:   0, Cs0width=x8
78 # bit3-2:   3, Cs0size=1Gbit
79 # bit5-4:   0, Cs1width=nonexistent
80 # bit7-6:   0, Cs1size=nonexistent
81 # bit9-8:   0, Cs2width=nonexistent
82 # bit11-10: 0, Cs2size=nonexistent
83 # bit13-12: 0, Cs3width=nonexistent
84 # bit15-14: 0, Cs3size=nonexistent
89 # bit31-20: 0 required
94 # bit31-1: 0 required
98 # bit3-0:   0, Cmd=Normal SDRAM Mode
99 # bit31-4:  0 required
103 # bit2-0:   2, Burst Length (2 required)
105 # bit6-4:   5, CAS Latency (CL) 5
108 # bit11-9:  3, Write recovery for auto-precharge (3 required)
110 # bit31-13: 0 required
117 # bit5-3:   0 required
119 # bit9-7:   0 required
123 # bit31-13: 0 required
127 # bit2-0:   0x7 required
129 # bit6-4:   0x7 required
135 # bit15-12: 0xf required
136 # bit31-16: 0 required
140 # bit3-0:   0 required
141 # bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
142 # bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
145 # bit31-20: 0 required
149 # bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
150 # bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
153 # bit31-16: 0 required
163 # bit3-2:   0x0, CS0 hit selected
164 # bit23-4:  0xfffff required
165 # bit31-24: 0x0f, Size (i.e. 256MB)
181 # bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
182 # bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
183 # bit15-8:  0 required
184 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
185 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
186 # bit31-24: 0 required
190 # bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
191 # bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
192 # bit31-4   0 required
196 # bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
197 # bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
198 # bit9-8:   0, Internal ODT assertion is controlled by fiels
199 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
200 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
203 # bit20-16: 0, Pad N channel driving strength for ODT
204 # bit25-21: 0, Pad P channel driving strength for ODT
205 # bit31-26: 0 required
210 # bit31-1:  0, required