Lines Matching refs:bit3

39 # bit3-0:   0 required
57 # bit3-0:   0xf, 16 cycle tRAS (tRAS[3-0])
78 # bit3-2:   2, Cs0size=512Mbit
98 # bit3-0:   0, Cmd=Normal SDRAM Mode
104 # bit3:     0, Burst Type (0 required)
128 # bit3:     1, MBUS Burst Chop disabled
140 # bit3-0:   0 required
149 # bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
163 # bit3-2:   0x0, CS0 hit selected
181 # bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
191 # bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
196 # bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3