Lines Matching +full:0 +full:x00000042
17 # Configure RGMII-0/1 interface pad voltage to 1.8V
18 DATA 0xFFD100E0 0x1B1B1B9B
20 # L2 RAM Timing 0
21 DATA 0xFFD20134 0xBBBBBBBB
25 DATA 0xFFD20138 0x00BBBBBB
29 DATA 0xFFD01400 0x43000618
30 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
31 # bit23-14: 0 required
34 # bit29-26: 0 required
35 # bit31-30: 0b01 required
38 DATA 0xFFD01404 0x39543000
39 # bit3-0: 0 required
40 # bit4: 0, addr/cmd in same cycle
41 # bit5: 0, clk is driven during self refresh, we don't care for APX
42 # bit6: 0, use recommended falling edge of clk for addr/cmd
43 # bit11-7: 0 required
46 # bit14: 0, input buffer always powered up
47 # bit17-15: 0 required
49 # bit19: 0 required
50 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
53 # bit31: 0, no additional STARTBURST delay
56 DATA 0xFFD01408 0x3302444F
57 # bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
62 # bit20: 0, 16 cycle tRAS (tRAS[4])
63 # bit23-21: 0 required
68 DATA 0xFFD0140C 0x00000823
69 # bit6-0: 0x23, 35 cycle tRFC
70 # bit8-7: 0, 1 cycle tR2R
71 # bit10-9: 0, 1 cyle tR2W
73 # bit31-13: 0 required
76 DATA 0xFFD01410 0x00000009
77 # bit1-0: 1, Cs0width=x16
79 # bit5-4: 0, Cs1width=nonexistent
80 # bit7-6: 0, Cs1size=nonexistent
81 # bit9-8: 0, Cs2width=nonexistent
82 # bit11-10: 0, Cs2size=nonexistent
83 # bit13-12: 0, Cs3width=nonexistent
84 # bit15-14: 0, Cs3size=nonexistent
85 # bit16: 0, Cs0AddrSel
86 # bit17: 0, Cs1AddrSel
87 # bit18: 0, Cs2AddrSel
88 # bit19: 0, Cs3AddrSel
89 # bit31-20: 0 required
92 DATA 0xFFD01414 0x00000000
93 # bit0: 0, OPEn=OpenPage enabled
94 # bit31-1: 0 required
97 DATA 0xFFD01418 0x00000000
98 # bit3-0: 0, Cmd=Normal SDRAM Mode
99 # bit31-4: 0 required
102 DATA 0xFFD0141C 0x00000652
103 # bit2-0: 2, Burst Length (2 required)
104 # bit3: 0, Burst Type (0 required)
106 # bit7: 0, (Test Mode) Normal operation
107 # bit8: 0, (Reset DLL) Normal operation
109 # bit12: 0, Fast Active power down exit time (0 required)
110 # bit31-13: 0 required
113 DATA 0xFFD01420 0x00000042
114 # bit0: 0, DRAM DLL enabled
116 # bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
117 # bit5-3: 0 required
119 # bit9-7: 0 required
120 # bit10: 0, differential DQS enabled
121 # bit11: 0 required
122 # bit12: 0, DRAM output buffer enabled
123 # bit31-13: 0 required
126 DATA 0xFFD01424 0x0000F17F
127 # bit2-0: 0x7 required
129 # bit6-4: 0x7 required
130 # bit7: 0 required (???)
132 # bit9: 0, no half clock cycle addition to dataout
133 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
134 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
135 # bit15-12: 0xf required
136 # bit31-16: 0 required
139 DATA 0xFFD01428 0x00085520
140 # bit3-0: 0 required
145 # bit31-20: 0 required
148 DATA 0xFFD0147C 0x00008552
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
153 # bit31-16: 0 required
155 # CS[0]n Base address
156 DATA 0xFFD01500 0x00000000
157 # at 0x0
159 # CS[0]n Size
160 DATA 0xFFD01504 0x03FFFFF1
162 # bit1: 0, Write Protect disabled
163 # bit3-2: 0x0, CS0 hit selected
164 # bit23-4: 0xfffff required
165 # bit31-24: 0x03, Size (i.e. 64MB)
168 DATA 0xFFD0150C 0x00000000
172 DATA 0xFFD01514 0x00000000
176 DATA 0xFFD0151C 0x00000000
180 DATA 0xFFD01494 0x003C0000
181 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
182 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
183 # bit15-8: 0 required
184 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
185 # bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
186 # bit31-24: 0 required
189 DATA 0xFFD01498 0x00000000
190 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
191 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
192 # bit31-4 0 required
195 DATA 0xFFD0149C 0x0000E80F
196 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
197 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
198 # bit9-8: 0, Internal ODT assertion is controlled by fiels
203 # bit20-16: 0, Pad N channel driving strength for ODT
204 # bit25-21: 0, Pad P channel driving strength for ODT
205 # bit31-26: 0 required
208 DATA 0xFFD01480 0x00000001
210 # bit31-1: 0, required
213 DATA 0x0 0x0