27 	return 0;  in checkboard()
42 	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,  in dram_init()
44 	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,  in dram_init()
51 	__raw_writel(0x33211530, &sdp->cfg1);  in dram_init()
52 	__raw_writel(0x56570000, &sdp->cfg2);  in dram_init()
54 	__raw_writel(0xE1462C02, &sdp->ctrl);  in dram_init()
57 	__raw_writel(0xE1462C04, &sdp->ctrl);  in dram_init()
59 	__raw_writel(0xE1462C04, &sdp->ctrl);  in dram_init()
61 	__raw_writel(0x008D0000, &sdp->mode);  in dram_init()
63 	__raw_writel(0x80010000, &sdp->mode);  in dram_init()
70 	__raw_writel(0x71462C00, &sdp->ctrl);  in dram_init()
72 	writel(0, CONFIG_SYS_SDRAM_BASE);  in dram_init()
79 	 * (Do not rely on the SDCS register(s) being set to 0x00000000  in dram_init()
83 				0x80000000 - CONFIG_SYS_SDRAM_BASE);  in dram_init()
85 	return 0;  in dram_init()
95 	case 0:  in rs_serial_init()
117 	writeb(0, &uart->uimr);  in rs_serial_init()
130 	writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);  in rs_serial_init()
132 	writeb((u8) (counter & 0x00ff), &uart->ubg2);  in rs_serial_init()
136 	return 0;  in rs_serial_init()
149 	timer = get_timer(0);  in astro_put_char()
178 	int retval = 0;  in misc_init_r()