Lines Matching refs:ldr
23 ldr r0, =GPCR
24 ldr r1, =ACFG_GPCR_VAL
25 ldr r5, [r0]
32 ldr r0, =CSCR
34 ldr r1, [r0]
65 ldr r0, =IMX_ESD_BASE
66 ldr r4, =ESDMISC_SDRAM_RDY
67 2: ldr r1, [r0, #ESDMISC_ROF]
72 ldr r0, =IMX_ESD_BASE
73 ldr r4, =ACFG_ESDMISC_VAL
78 ldr r1, =0x10000
84 ldr r0, =IMX_ESD_BASE
85 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
88 ldr r0, =IMX_ESD_BASE
89 ldr r1, =ACFG_PRECHARGE_CMD
93 ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
96 ldr r1, =ACFG_AUTOREFRESH_CMD
99 ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
101 ldr r6,=0x7 /* load loop counter */
106 ldr r1, =ACFG_SET_MODE_REG_CMD
110 ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
114 ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
117 ldr r1, =ACFG_NORMAL_RW_CMD
121 ldr r0, =IMX_ESD_BASE
122 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
125 ldr r0, =IMX_ESD_BASE
126 ldr r1, =ACFG_PRECHARGE_CMD
130 ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
133 ldr r1, =ACFG_AUTOREFRESH_CMD
136 ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
138 ldr r6,=0x7 /* load loop counter */
143 ldr r1, =ACFG_SET_MODE_REG_CMD
147 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
151 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
154 ldr r1, =ACFG_NORMAL_RW_CMD