armadeus/apf27/apf27.h

28  * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
34 #define ACFG_CLK_FREQ	(CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
45 #define CONFIG_HCLK_FREQ	133	/* (ACFG_CLK_FREQ/2) */
76 					    * 2=4096 3=8192 refresh
78 #define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
84 #define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
85 #define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
88 #define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
89 					    * SDRAM: 0=1ck 1=2ck
91 #define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
92 #define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
93 #define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
94 #define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
97 #define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
101 #define ACFG_SDRAM_PARTIAL_ARRAY_SR	0  /* 0=full 1=half 2=quater
105 					    * 2=quater 3=Eighth
107 #define ACFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
122 					    * 2=4096 3=8192 refresh
124 #define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
130 #define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
131 #define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
134 #define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
135 					    * SDRAM: 0=1ck 1=2ck
137 #define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
138 #define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
139 #define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
140 #define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
143 #define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
147 #define ACFG_SDRAM_PARTIAL_ARRAY_SR	0  /* 0=full 1=half 2=quater
151 					    * 2=quater 3=Eighth
153 #define ACFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
168 					    * 2=4096 3=8192 refresh
170 #define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
176 #define ACFG_SDRAM_ROW_PRECHARGE_DELAY	18 /* ns */
177 #define ACFG_SDRAM_TMRD_DELAY		2  /* Load mode register
180 #define ACFG_SDRAM_TWR_DELAY		1  /* LPDDR: 0=2ck 1=3ck
181 					    * SDRAM: 0=1ck 1=2ck
183 #define ACFG_SDRAM_RAS_DELAY		42 /* ns ACTIVE-to-PRECHARGE delay */
184 #define ACFG_SDRAM_RRD_DELAY		12 /* ns ACTIVE-to-ACTIVE delay */
185 #define ACFG_SDRAM_RCD_DELAY		18 /* ns Row to Column delay */
186 #define ACFG_SDRAM_RC_DELAY		70 /* ns Row cycle delay (tRFC
189 #define ACFG_SDRAM_CLOCK_CYCLE_CL_1	0 /* ns clock cycle time
193 #define ACFG_SDRAM_PARTIAL_ARRAY_SR	0  /* 0=full 1=half 2=quater
198 					    * 2=quater
201 #define ACFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
266 /* drive strength CLKO set to 2 */
268 /* drive strength A1..A12 set to 2 */
374 /* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
377 #elif (CONFIG_NR_DRAM_BANKS == 2)
395 /* fixme none integer value (7.5ns) => 2*hclock = 15ns */
396 #define ACFG_2XHCLK_LGTH	(2000/CONFIG_HCLK_FREQ)	/* ns */
411 	|(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\
412 	|(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\
415 	|(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26))
425 #if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \
431 	((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \
436 #if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH))
440 	((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \
457 	| (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \
460 	| (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \
464 	| (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \
466 	| (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
469 	| (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
484 	| (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2)))