Lines Matching +full:0 +full:x00000009
25 #define DS414_GPP_OUT_VAL_HIGH (0)
27 #define DS414_GPP_OUT_POL_LOW (0)
28 #define DS414_GPP_OUT_POL_MID (0)
29 #define DS414_GPP_OUT_POL_HIGH (0)
34 #define DS414_GPP_OUT_ENA_HIGH (~0)
37 0x11111111,
38 0x22221111,
39 0x22222222,
40 0x00000000,
41 0x11110000,
42 0x00004000,
43 0x00000000,
44 0x00000000,
45 0x00000000
52 {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
53 {0x00001404, 0x30000800}, /*Dunit Control Low Register */
54 {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */
55 {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */
57 {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */
59 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
60 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
61 {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
62 {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */
63 {0x00001428, 0x000F8830}, /*Dunit Control High Register */
64 {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */
65 {0x0000147C, 0x0000C671},
67 {0x000014a0, 0x00000001},
68 {0x000014a8, 0x00000100}, /*2:1 */
69 {0x00020220, 0x00000006},
71 {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
72 {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
73 {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */
75 {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
76 {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
78 …{0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the trai…
79 {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
81 {0x0001504, 0x3FFFFFE1}, /* CS0 Size */
82 {0x000150C, 0x00000000}, /* CS1 Size */
83 {0x0001514, 0x00000000}, /* CS2 Size */
84 {0x000151C, 0x00000000}, /* CS3 Size */
86 {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
87 {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */
89 {0x000015D0, 0x00000650}, /*MR0 */
90 {0x000015D4, 0x00000044}, /*MR1 */
91 {0x000015D8, 0x00000010}, /*MR2 */
92 {0x000015DC, 0x00000000}, /*MR3 */
94 {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
95 {0x000015EC, 0xF800A225}, /*DDR PHY */
97 {0x0, 0x0}
101 {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
107 { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
110 0x0040, serdes_change_m_phy
116 return &ds414_ddr_modes[0]; in ddr3_get_static_ddr_mode()
121 return &ds414_serdes_cfg[0]; in board_serdes_cfg_get()
126 return (0x1 << 1 | 1); in board_sat_r_get()
134 reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); in board_early_init_f()
139 reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); in board_early_init_f()
144 reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); in board_early_init_f()
148 for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++) in board_early_init_f()
151 return 0; in board_early_init_f()
159 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; in board_init()
168 pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */ in board_init()
177 return 0; in board_init()
184 return 0; in checkboard()