Lines Matching +full:0 +full:x00000042
21 # Configure RGMII-0/1 interface pad voltage to 1.8V
22 DATA 0xFFD100e0 0x1b1b1b9b
24 DATA 0xFFD20134 0xbbbbbbbb
25 DATA 0xFFD20138 0x00bbbbbb
28 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
29 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
36 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
37 # bit 4: 0=addr/cmd in smame cycle
38 # bit 5: 0=clk is driven during self refresh, we don't care for APX
39 # bit 6: 0=use recommended falling edge of clk for addr/cmd
40 # bit14: 0=input buffer always powered up
42 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
45 # bit31: 0=no additional STARTBURST delay
47 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
48 # bit3-0: TRAS lsbs
54 # bit23-21: 0x0
58 DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
59 # bit6-0: TRFC
65 DATA 0xFFD01410 0x0000000d # DDR Address Control
66 # bit1-0: 01, Cs0width=x8
74 # bit16: 0, Cs0AddrSel
75 # bit17: 0, Cs1AddrSel
76 # bit18: 0, Cs2AddrSel
77 # bit19: 0, Cs3AddrSel
78 # bit31-20: 0 required
80 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
81 # bit0: 0, OpenPage enabled
82 # bit31-1: 0 required
84 DATA 0xFFD01418 0x00000000 # DDR Operation
85 # bit3-0: 0x0, DDR cmd
86 # bit31-4: 0 required
88 DATA 0xFFD0141C 0x00000C52 # DDR Mode
89 # bit2-0: 2, BurstLen=2 required
90 # bit3: 0, BurstType=0 required
92 # bit7: 0, TestMode=0 normal
93 # bit8: 0, DLL reset=0 normal
95 # bit12: 0, PD must be zero
96 # bit31-13: 0 required
98 DATA 0xFFD01420 0x00000042 # DDR Extended Mode
99 # bit0: 0, DDR DLL enabled
100 # bit1: 0, DDR drive strenght normal
101 # bit2: 0, DDR ODT control lsd (disabled)
105 # bit10: 0, differential DQS enabled
106 # bit11: 0, required
107 # bit12: 0, DDR output buffer enabled
108 # bit31-13: 0 required
110 DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
111 # bit2-0: 111, required
114 # bit7 : 0
116 # bit9 : 0 , no half clock cycle addition to dataout
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
120 # bit31-16: 0 required
122 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
123 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
125 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
126 DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
128 # bit1: 0, Write Protect disabled
131 # bit31-24: 0x07, Size (i.e. 128MB)
133 DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
134 DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
136 DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb
137 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
138 DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb
139 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
141 DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
142 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
143 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
147 DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
148 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
152 DATA 0x0 0x0