Lines Matching +full:self +full:- +full:powered

12 # SPDX-License-Identifier:	GPL-2.0+
14 # Refer docs/README.kwimage for more details about how-to configure
26 # Configure RGMII-0 interface pad voltage to 1.8V
31 # bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
32 # bit23-14: zero
33 # bit24: 1= enable exit self refresh mode on DDR access
35 # bit29-26: zero
36 # bit31-30: 01
40 # bit 5:    0=clk is driven during self refresh, we don't care for APX
42 # bit14:    0=input buffer always powered up
44 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
45 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
46 # bit30-28: 3 required
50 # bit3-0:   TRAS lsbs
51 # bit7-4:   TRCD
52 # bit11- 8: TRP
53 # bit15-12: TWR
54 # bit19-16: TWTR
56 # bit23-21: 0x0
57 # bit27-24: TRRD
58 # bit31-28: TRTP
61 # bit6-0:   TRFC
62 # bit8-7:   TR2R
63 # bit10-9:  TR2W
64 # bit12-11: TW2W
65 # bit31-13: zero required
68 # bit1-0:   00, Cs0width=x8
69 # bit3-2:   11, Cs0size=1Gb
70 # bit5-4:   00, Cs1width=nonexistent
71 # bit7-6:   00, Cs1size =nonexistent
72 # bit9-8:   00, Cs2width=nonexistent
73 # bit11-10: 00, Cs2size =nonexistent
74 # bit13-12: 00, Cs3width=nonexistent
75 # bit15-14: 00, Cs3size =nonexistent
80 # bit31-20: 0 required
84 # bit31-1: 0 required
87 # bit3-0:   0x0, DDR cmd
88 # bit31-4:  0 required
91 # bit2-0:   2, BurstLen=2 required
93 # bit6-4:   4, CL=5
96 # bit11-9:  6, auto-precharge write recovery ????????????
98 # bit31-13: 0 required
104 # bit5-3:  000, required
106 # bit9-7:  000, required
110 # bit31-13: 0 required
113 # bit2-0:  111, required
115 # bit6-4:  111, required
121 # bit15-12: 1111 required
122 # bit31-16: 0    required
131 # bit3-2:  00, CS0 hit selected
132 # bit23-4: ones, required
133 # bit31-24: 0x07, Size (i.e. 128MB)
143 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
144 # bit3-2:  01, ODT1 active NEVER!
145 # bit31-4: zero, required