Marvell/guruplug/kwbimage.cfg

4 # Written-by: Siddarth Gore <gores@marvell.com>
6 # SPDX-License-Identifier:	GPL-2.0+
8 # Refer doc/README.kwbimage for more details about how-to configure
20 # Configure RGMII-0/1 interface pad voltage to 1.8V
25 # bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
26 # bit23-14: zero
27 # bit24: 1= enable exit self refresh mode on DDR access
29 # bit29-26: zero
30 # bit31-30: 01
34 # bit 5:    0=clk is driven during self refresh, we don't care for APX
36 # bit14:    0=input buffer always powered up
38 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
39 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
40 # bit30-28: 3 required
44 # bit3-0:   TRAS lsbs
45 # bit7-4:   TRCD
46 # bit11- 8: TRP
47 # bit15-12: TWR
48 # bit19-16: TWTR
50 # bit23-21: 0x0
51 # bit27-24: TRRD
52 # bit31-28: TRTP
55 # bit6-0:   TRFC
56 # bit8-7:   TR2R
57 # bit10-9:  TR2W
58 # bit12-11: TW2W
59 # bit31-13: zero required
62 # bit1-0:   01, Cs0width=x8
63 # bit3-2:   10, Cs0size=1Gb
64 # bit5-4:   01, Cs1width=x8
65 # bit7-6:   10, Cs1size=1Gb
66 # bit9-8:   00, Cs2width=nonexistent
67 # bit11-10: 00, Cs2size =nonexistent
68 # bit13-12: 00, Cs3width=nonexistent
69 # bit15-14: 00, Cs3size =nonexistent
74 # bit31-20: 0 required
78 # bit31-1: 0 required
81 # bit3-0:   0x0, DDR cmd
82 # bit31-4:  0 required
85 # bit2-0:   2, BurstLen=2 required
87 # bit6-4:   4, CL=5
90 # bit11-9:  6, auto-precharge write recovery ????????????
92 # bit31-13: 0 required
98 # bit5-3:  000, required
100 # bit9-7:  000, required
104 # bit31-13: 0 required
107 # bit2-0:  111, required
109 # bit6-4:  111, required
115 # bit15-12: 1111 required
116 # bit31-16: 0    required
125 # bit3-2:  00, CS0 hit selected
126 # bit23-4: ones, required
127 # bit31-24: 0x0F, Size (i.e. 256MB)
137 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
138 # bit3-2:  01, ODT1 active NEVER!
139 # bit31-4: zero, required