Lines Matching +full:0 +full:x00000044
21 # Configure RGMII-0 interface pad voltage to 1.8V
22 DATA 0xFFD100e0 0x1B1B1B9B
25 DATA 0xFFD01400 0x43000C30 # DDR Configuration register
26 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
33 DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
34 # bit 4: 0=addr/cmd in smame cycle
35 # bit 5: 0=clk is driven during self refresh, we don't care for APX
36 # bit 6: 0=use recommended falling edge of clk for addr/cmd
37 # bit14: 0=input buffer always powered up
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
42 # bit31: 0=no additional STARTBURST delay
44 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
50 # bit23-21: 0x0
54 DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
55 # bit6-0: TRFC
61 DATA 0xFFD01410 0x0000CCCC # DDR Address Control
62 # bit1-0: 01, Cs0width=x16
70 # bit16: 0, Cs0AddrSel
71 # bit17: 0, Cs1AddrSel
72 # bit18: 0, Cs2AddrSel
73 # bit19: 0, Cs3AddrSel
74 # bit31-20: 0 required
76 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
77 # bit0: 0, OpenPage enabled
78 # bit31-1: 0 required
80 DATA 0xFFD01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
82 # bit31-4: 0 required
84 DATA 0xFFD0141C 0x00000662 # DDR Mode
85 # bit2-0: 2, BurstLen=2 required
86 # bit3: 0, BurstType=0 required
88 # bit7: 0, TestMode=0 normal
89 # bit8: 0, DLL reset=0 normal
91 # bit12: 0, PD must be zero
92 # bit31-13: 0 required
94 DATA 0xFFD01420 0x00000044 # DDR Extended Mode
95 # bit0: 0, DDR DLL enabled
101 # bit10: 0, differential DQS enabled
102 # bit11: 0, required
103 # bit12: 0, DDR output buffer enabled
104 # bit31-13: 0 required
106 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
107 # bit2-0: 111, required
112 # bit9 : 0 , no half clock cycle addition to dataout
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
116 # bit31-16: 0 required
118 DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
119 DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
121 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
122 DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
124 # bit1: 0, Write Protect disabled
127 # bit31-24: 0x07, Size (i.e. 128MB)
129 DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
130 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
131 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
133 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
135 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
137 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
138 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
142 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
147 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
151 DATA 0x0 0x0