Lines Matching +full:0 +full:x4001
11 #define MSG_PORT_MEM_ARBITER 0x00
12 #define MSG_PORT_HOST_BRIDGE 0x03
13 #define MSG_PORT_RMU 0x04
14 #define MSG_PORT_MEM_MGR 0x05
15 #define MSG_PORT_USB_AFE 0x14
16 #define MSG_PORT_PCIE_AFE 0x16
17 #define MSG_PORT_SOC_UNIT 0x31
19 /* Port 0x00: Memory Arbiter Message Port Registers */
22 #define AEC_CTRL 0x00
24 /* Port 0x03: Host Bridge Message Port Registers */
27 #define HMISC2 0x03
29 #define HMISC2_SEGE 0x00000002
30 #define HMISC2_SEGF 0x00000004
31 #define HMISC2_SEGAB 0x00000010
34 #define HM_BOUND 0x08
35 #define HM_BOUND_LOCK 0x00000001
38 #define HEC_REG 0x09
41 #define MTRR_CAP 0x40
42 #define MTRR_DEF_TYPE 0x41
44 #define MTRR_FIX_64K_00000 0x42
45 #define MTRR_FIX_64K_40000 0x43
46 #define MTRR_FIX_16K_80000 0x44
47 #define MTRR_FIX_16K_90000 0x45
48 #define MTRR_FIX_16K_A0000 0x46
49 #define MTRR_FIX_16K_B0000 0x47
50 #define MTRR_FIX_4K_C0000 0x48
51 #define MTRR_FIX_4K_C4000 0x49
52 #define MTRR_FIX_4K_C8000 0x4a
53 #define MTRR_FIX_4K_CC000 0x4b
54 #define MTRR_FIX_4K_D0000 0x4c
55 #define MTRR_FIX_4K_D4000 0x4d
56 #define MTRR_FIX_4K_D8000 0x4e
57 #define MTRR_FIX_4K_DC000 0x4f
58 #define MTRR_FIX_4K_E0000 0x50
59 #define MTRR_FIX_4K_E4000 0x51
60 #define MTRR_FIX_4K_E8000 0x52
61 #define MTRR_FIX_4K_EC000 0x53
62 #define MTRR_FIX_4K_F0000 0x54
63 #define MTRR_FIX_4K_F4000 0x55
64 #define MTRR_FIX_4K_F8000 0x56
65 #define MTRR_FIX_4K_FC000 0x57
67 #define MTRR_SMRR_PHYBASE 0x58
68 #define MTRR_SMRR_PHYMASK 0x59
70 #define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n))
71 #define MTRR_VAR_PHYMASK(n) (0x5b + 2 * (n))
84 /* Port 0x04: Remote Management Unit Message Port Registers */
87 #define PBLK_BA 0x70
90 #define RMU_CTRL 0x71
93 #define SPI_DMA_BA 0x7a
96 #define TS_MODE 0xb0
97 #define TS_TEMP 0xb1
98 #define TS_TRIP 0xb2
100 /* Port 0x05: Memory Manager Message Port Registers */
103 #define ESRAM_BLK_CTRL 0x82
104 #define ESRAM_BLOCK_MODE 0x10000000
106 /* Port 0x14: USB2 AFE Unit Port Registers */
108 #define USB2_GLOBAL_PORT 0x4001
109 #define USB2_PLL1 0x7f02
110 #define USB2_PLL2 0x7f03
111 #define USB2_COMPBG 0x7f04
113 /* Port 0x16: PCIe AFE Unit Port Registers */
115 #define PCIE_RXPICTRL0_L0 0x2080
116 #define PCIE_RXPICTRL0_L1 0x2180
118 /* Port 0x31: SoC Unit Port Registers */
121 #define TS_CFG1 0x31
122 #define TS_CFG2 0x32
123 #define TS_CFG3 0x33
124 #define TS_CFG4 0x34
127 #define PCIE_CFG 0x36
128 #define PCIE_CTLR_PRI_RST 0x00010000
129 #define PCIE_PHY_SB_RST 0x00020000
130 #define PCIE_CTLR_SB_RST 0x00040000
131 #define PCIE_PHY_LANE_RST 0x00090000
132 #define PCIE_CTLR_MAIN_RST 0x00100000
135 #define DRAM_BASE 0x00000000
136 #define DRAM_MAX_SIZE 0x80000000
139 #define ESRAM_SIZE 0x80000
142 #define MEM_BAR_EN 0x00000001
145 #define IO_BAR_EN 0x80000000
148 #define RMU_BINARY_SIZE 0x10000
152 #define PCIE_RP_CCFG 0xd0
158 #define PCIE_RP_MPC2 0xd4
161 #define PCIE_RP_MBC 0xf4
165 #define LB_GBA 0x44
166 #define LB_PM1BLK 0x48
167 #define LB_GPE0BLK 0x4c
168 #define LB_ACTL 0x58
169 #define LB_PABCDRC 0x60
170 #define LB_PEFGHRC 0x64
171 #define LB_WDTBA 0x84
172 #define LB_BCE 0xd4
173 #define LB_BC 0xd8
174 #define LB_RCBA 0xf0
177 #define EHCI_INSNREG01 0x94
180 #define USBD_INT_MASK 0x410
181 #define USBD_EP_INT_STS 0x414
182 #define USBD_EP_INT_MASK 0x418