Lines Matching +full:native +full:- +full:mode
1 /dts-v1/;
3 #include <dt-bindings/gpio/x86-gpio.h>
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "intel,core-i3-gen5";
34 intel,apic-id = <0>;
35 intel,slow-ramp = <3>;
40 compatible = "intel,core-i3-gen5";
42 intel,apic-id = <1>;
47 compatible = "intel,core-i3-gen5";
49 intel,apic-id = <2>;
54 compatible = "intel,core-i3-gen5";
56 intel,apic-id = <3>;
62 stdout-path = "/serial";
66 intel,duplicate-por;
70 compatible = "intel,x86-broadwell-pinctrl";
71 u-boot,dm-pre-reloc;
75 gpio_unused: gpio-unused {
76 mode-gpio;
79 sense-disable;
82 gpio_acpi_sci: acpi-sci {
83 mode-gpio;
89 gpio_acpi_smi: acpi-smi {
90 mode-gpio;
96 gpio_input: gpio-input {
97 mode-gpio;
102 gpio_input_invert: gpio-input-invert {
103 mode-gpio;
109 gpio_native: gpio-native {
112 gpio_out_high: gpio-out-high {
113 mode-gpio;
115 output-value = <1>;
117 sense-disable;
120 gpio_out_low: gpio-out-low {
121 mode-gpio;
123 output-value = <0>;
125 sense-disable;
128 gpio_pirq: gpio-pirq {
129 mode-gpio;
132 pirq-apic = <PIRQ_APIC_ROUTE>;
141 <4 &gpio_native 0>, /* native: i2c0_sda_gpio4 */
142 <5 &gpio_native 0>, /* native: i2c0_scl_gpio5 */
143 <6 &gpio_native 0>, /* native: i2c1_sda_gpio6 */
144 <7 &gpio_native 0>, /* native: i2c1_scl_gpio7 */
167 <30 &gpio_native 0>, /* native: pch_suswarn_l */
168 <31 &gpio_native 0>, /* native: acok_buf */
169 <32 &gpio_native 0>, /* native: lpc_clkrun_l */
170 <33 &gpio_native 0>, /* native: ssd_devslp */
177 <40 &gpio_native 0>, /* native: pch_usb1_oc_l */
178 <41 &gpio_native 0>, /* native: pch_usb2_oc_l */
182 <45 &gpio_acpi_sci 0>, /* dsp_int - codec wake */
183 <46 &gpio_pirq 6>, /* hotword_det_l_3v3 (pirqo) - codec irq */
198 <61 &gpio_native 0>, /* native: pch_sus_stat */
199 <62 &gpio_native 0>, /* native: pch_susclk */
200 <63 &gpio_native 0>, /* native: pch_slp_s5_l */
208 <71 &gpio_native 0>, /* native: modphy_en */
219 <82 &gpio_native 0>, /* native: ec_rcin_l */
236 compatible = "pci-x86";
237 #address-cells = <3>;
238 #size-cells = <2>;
239 u-boot,dm-pre-reloc;
246 compatible = "intel,broadwell-northbridge";
247 board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
249 u-boot,dm-pre-reloc;
251 #address-cells = <1>;
252 #size-cells = <0>;
288 hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
362 hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
401 hynix-h9ccnnncltmlar-lpddr3 {
440 elpida-edfb232a1ma {
484 compatible = "intel,broadwell-igd";
485 intel,dp-hotplug = <6 6 6>;
486 intel,port-select = <1>; /* eDP */
487 intel,power-cycle-delay = <6>;
488 intel,power-up-delay = <2000>;
489 intel,power-down-delay = <500>;
490 intel,power-backlight-on-delay = <2000>;
491 intel,power-backlight-off-delay = <2000>;
492 intel,cpu-backlight = <0x00000200>;
493 intel,pch-backlight = <0x04000200>;
494 intel,pre-graphics-delay = <200>;
500 u-boot,dm-pre-reloc;
505 compatible = "xhci-pci";
511 compatible = "ehci-pci";
516 compatible = "intel,broadwell-pch";
517 u-boot,dm-pre-reloc;
518 #address-cells = <1>;
519 #size-cells = <1>;
520 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
522 intel,gpi-routing = <0 0 0 0 0 0 0 2
525 intel,alt-gp-smi-enable = <0x0040>;
527 /* EC-SCI is GPIO36 */
528 intel,gpe0-en = <0 0x10 0 0>;
530 power-enable-gpio = <&gpio_a 23 0>;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "intel,ich9-spi";
536 spi-flash@0 {
537 #size-cells = <1>;
538 #address-cells = <1>;
541 "spi-flash";
542 memory-map = <0xff800000 0x00800000>;
543 rw-mrc-cache {
544 label = "rw-mrc-cache";
551 compatible = "intel,broadwell-gpio";
552 u-boot,dm-pre-reloc;
553 #gpio-cells = <2>;
554 gpio-controller;
556 bank-name = "A";
560 compatible = "intel,broadwell-gpio";
561 u-boot,dm-pre-reloc;
562 #gpio-cells = <2>;
563 gpio-controller;
565 bank-name = "B";
569 compatible = "intel,broadwell-gpio";
570 u-boot,dm-pre-reloc;
571 #gpio-cells = <2>;
572 gpio-controller;
574 bank-name = "C";
578 compatible = "intel,broadwell-lpc";
579 #address-cells = <1>;
580 #size-cells = <0>;
581 u-boot,dm-pre-reloc;
582 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
583 cros-ec@200 {
584 compatible = "google,cros-ec-lpc";
591 #address-cells = <1>;
592 #size-cells = <1>;
595 erase-value = <0xff>;
602 compatible = "intel,wildcatpoint-ahci";
604 u-boot,dm-pre-reloc;
605 intel,sata-mode = "ahci";
606 intel,sata-port-map = <1>;
607 intel,sata-port0-gen3-tx = <0x72>;
608 reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>;
612 compatible = "intel,ich-i2c";
614 u-boot,dm-pre-reloc;