x86/dts/bayleybay.dts

4  * SPDX-License-Identifier:	GPL-2.0+
7 /dts-v1/;
9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
34 		stdout-path = "/serial";
38 		#address-cells = <1>;
39 		#size-cells = <0>;
41 		cpu@0 {
42 			device_type = "cpu";
43 			compatible = "intel,baytrail-cpu";
45 			intel,apic-id = <0>;
48 		cpu@1 {
49 			device_type = "cpu";
50 			compatible = "intel,baytrail-cpu";
52 			intel,apic-id = <2>;
55 		cpu@2 {
56 			device_type = "cpu";
57 			compatible = "intel,baytrail-cpu";
59 			intel,apic-id = <4>;
62 		cpu@3 {
63 			device_type = "cpu";
64 			compatible = "intel,baytrail-cpu";
66 			intel,apic-id = <6>;
71 		compatible = "intel,x86-pinctrl";
85 			pad-offset = <0x3a0>;
86 			mode-func = <1>;
91 		compatible = "pci-x86";
92 		#address-cells = <3>;
93 		#size-cells = <2>;
94 		u-boot,dm-pre-reloc;
102 			#address-cells = <1>;
103 			#size-cells = <1>;
105 			irq-router {
106 				compatible = "intel,irq-router";
107 				intel,pirq-config = "ibase";
108 				intel,ibase-offset = <0x50>;
109 				intel,actl-addr = <0>;
110 				intel,pirq-link = <8 8>;
111 				intel,pirq-mask = <0xdee0>;
112 				intel,pirq-routing = <
125 					PCI_BDF(0, 24, 1) INTC PIRQC
129 					PCI_BDF(0, 24, 5) INTC PIRQC
136 					PCI_BDF(0, 28, 2) INTC PIRQC
142 					PCI_BDF(0, 30, 3) INTC PIRQC
153 					PCI_BDF(1, 0, 0) INTC PIRQC
157 					PCI_BDF(2, 0, 0) INTC PIRQD
161 					PCI_BDF(3, 0, 0) INTC PIRQA
165 					PCI_BDF(4, 0, 0) INTC PIRQB
171 				#address-cells = <1>;
172 				#size-cells = <0>;
173 				compatible = "intel,ich9-spi";
174 				spi-flash@0 {
175 					#address-cells = <1>;
176 					#size-cells = <1>;
179 						"spi-flash";
180 					memory-map = <0xff800000 0x00800000>;
181 					rw-mrc-cache {
182 						label = "rw-mrc-cache";
189 				compatible = "intel,ich6-gpio";
190 				u-boot,dm-pre-reloc;
192 				bank-name = "A";
193 				use-lvl-write-cache;
197 				compatible = "intel,ich6-gpio";
198 				u-boot,dm-pre-reloc;
200 				bank-name = "B";
201 				use-lvl-write-cache;
205 				compatible = "intel,ich6-gpio";
206 				u-boot,dm-pre-reloc;
208 				bank-name = "C";
209 				use-lvl-write-cache;
213 				compatible = "intel,ich6-gpio";
214 				u-boot,dm-pre-reloc;
216 				bank-name = "D";
217 				use-lvl-write-cache;
221 				compatible = "intel,ich6-gpio";
222 				u-boot,dm-pre-reloc;
224 				bank-name = "E";
225 				use-lvl-write-cache;
229 				compatible = "intel,ich6-gpio";
230 				u-boot,dm-pre-reloc;
232 				bank-name = "F";
233 				use-lvl-write-cache;
239 		compatible = "intel,baytrail-fsp";
240 		fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
241 		fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
242 		fsp,mrc-init-spd-addr1 = <0xa0>;
243 		fsp,mrc-init-spd-addr2 = <0xa2>;
244 		fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
245 		fsp,enable-sdio;
246 		fsp,enable-sdcard;
247 		fsp,enable-hsuart1;
248 		fsp,enable-spi;
249 		fsp,enable-sata;
250 		fsp,sata-mode = <SATA_MODE_AHCI>;
251 		fsp,lpe-mode = <LPE_MODE_PCI>;
252 		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
253 		fsp,enable-dma0;
254 		fsp,enable-dma1;
255 		fsp,enable-i2c0;
256 		fsp,enable-i2c1;
257 		fsp,enable-i2c2;
258 		fsp,enable-i2c3;
259 		fsp,enable-i2c4;
260 		fsp,enable-i2c5;
261 		fsp,enable-i2c6;
262 		fsp,enable-pwm0;
263 		fsp,enable-pwm1;
264 		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
265 		fsp,aperture-size = <APERTURE_SIZE_256MB>;
266 		fsp,gtt-size = <GTT_SIZE_2MB>;
267 		fsp,scc-mode = <SCC_MODE_PCI>;
268 		fsp,os-selection = <OS_SELECTION_LINUX>;
269 		fsp,emmc45-ddr50-enabled;
270 		fsp,emmc45-retune-timer-value = <8>;
271 		fsp,enable-igd;