58 void clear_self_refresh(struct mrc_params *mrc_params)  in clear_self_refresh()  argument
69 void prog_ddr_timing_control(struct mrc_params *mrc_params)  in prog_ddr_timing_control()  argument
88 	tck = t_ck[mrc_params->ddr_speed];	/* Clock in picoseconds */  in prog_ddr_timing_control()
89 	tcl = mrc_params->params.cl;		/* CAS latency in clocks */  in prog_ddr_timing_control()
92 	tras = MCEIL(mrc_params->params.ras, tck);  in prog_ddr_timing_control()
97 	twtr = MCEIL(mrc_params->params.wtr, tck);  in prog_ddr_timing_control()
98 	trrd = MCEIL(mrc_params->params.rrd, tck);  in prog_ddr_timing_control()
100 	tfaw = MCEIL(mrc_params->params.faw, tck);  in prog_ddr_timing_control()
102 	wl = 5 + mrc_params->ddr_speed;  in prog_ddr_timing_control()
105 	dtr0 |= mrc_params->ddr_speed;  in prog_ddr_timing_control()
145 	if (mrc_params->ddr_speed == DDRFREQ_800) {  in prog_ddr_timing_control()
148 	} else if (mrc_params->ddr_speed == DDRFREQ_1066) {  in prog_ddr_timing_control()
157 	if (mrc_params->ddr_speed == DDRFREQ_800)  in prog_ddr_timing_control()
182 void prog_decode_before_jedec(struct mrc_params *mrc_params)  in prog_decode_before_jedec()  argument
220 	if (mrc_params->rank_enables & 1)  in prog_decode_before_jedec()
222 	if (mrc_params->rank_enables & 2)  in prog_decode_before_jedec()
236 void perform_ddr_reset(struct mrc_params *mrc_params)  in perform_ddr_reset()  argument
248 		       mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0);  in perform_ddr_reset()
258 void ddrphy_init(struct mrc_params *mrc_params)  in ddrphy_init()  argument
266 	uint8_t speed = mrc_params->ddr_speed & 3;  in ddrphy_init()
272 	cas = mrc_params->params.cl;  in ddrphy_init()
273 	cwl = 5 + mrc_params->ddr_speed;  in ddrphy_init()
286 		if (mrc_params->channel_enables & (1 << ch)) {  in ddrphy_init()
310 		if (mrc_params->channel_enables & (1 << ch)) {  in ddrphy_init()
323 				switch (mrc_params->rd_odt_value) {  in ddrphy_init()
404 				switch (mrc_params->rd_odt_value) {  in ddrphy_init()
848 				if (mrc_params->rank_enables & (1 << rk)) {  in ddrphy_init()
941 		if (mrc_params->channel_enables & (1 << ch)) {  in ddrphy_init()
977 		if (mrc_params->channel_enables & (1 << ch)) {  in ddrphy_init()
1013 		if (mrc_params->channel_enables & (1 << ch)) {  in ddrphy_init()
1020 					(mrc_params->channel_width == X16)) ?  in ddrphy_init()
1065 		if (mrc_params->channel_enables & (1 << ch)) {  in ddrphy_init()
1154 void perform_jedec_init(struct mrc_params *mrc_params)  in perform_jedec_init()  argument
1198 		if ((mrc_params->rank_enables & (1 << rank)) == 0)  in perform_jedec_init()
1205 		(mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0));  in perform_jedec_init()
1218 	wl = 5 + mrc_params->ddr_speed;  in perform_jedec_init()
1220 	emrs2_cmd |= (mrc_params->sr_temp_range << 13);  in perform_jedec_init()
1258 	if (mrc_params->ron_value == 0)  in perform_jedec_init()
1263 	if (mrc_params->rtt_nom_value == 0)  in perform_jedec_init()
1265 	else if (mrc_params->rtt_nom_value == 1)  in perform_jedec_init()
1267 	else if (mrc_params->rtt_nom_value == 2)  in perform_jedec_init()
1271 	mrc_params->mrs1 = emrs1_cmd >> 6;  in perform_jedec_init()
1300 	tck = t_ck[mrc_params->ddr_speed];  in perform_jedec_init()
1307 		if ((mrc_params->rank_enables & (1 << rank)) == 0)  in perform_jedec_init()
1337 void set_ddr_init_complete(struct mrc_params *mrc_params)  in set_ddr_init_complete()  argument
1357 void restore_timings(struct mrc_params *mrc_params)  in restore_timings()  argument
1360 	const struct mrc_timings *mt = &mrc_params->timings;  in restore_timings()
1386 void default_timings(struct mrc_params *mrc_params)  in default_timings()  argument
1408 void rcvn_cal(struct mrc_params *mrc_params)  in rcvn_cal()  argument
1413 	uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;  in rcvn_cal()
1452 		if (mrc_params->channel_enables & (1 << ch)) {  in rcvn_cal()
1455 				if (mrc_params->rank_enables & (1 << rk)) {  in rcvn_cal()
1484 					find_rising_edge(mrc_params, delay, ch, rk, true);  in rcvn_cal()
1493 						temp = sample_dqs(mrc_params, ch, rk, true);  in rcvn_cal()
1555 void wr_level(struct mrc_params *mrc_params)  in wr_level()  argument
1560 	uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;  in wr_level()
1598 		if (mrc_params->channel_enables & (1 << ch)) {  in wr_level()
1601 				if (mrc_params->rank_enables & (1 << rk)) {  in wr_level()
1664 					find_rising_edge(mrc_params, delay, ch, rk, false);  in wr_level()
1686 					dram_init_command(DCMD_MRS1(rk, mrc_params->mrs1));  in wr_level()
1702 					mrc_params->hte_setup = 1;  in wr_level()
1719 						uint32_t coarse_result_mask = byte_lane_mask(mrc_params);  in wr_level()
1723 						mrc_params->hte_setup = 1;  in wr_level()
1724 						coarse_result = check_rw_coarse(mrc_params, address);  in wr_level()
1758 void prog_page_ctrl(struct mrc_params *mrc_params)  in prog_page_ctrl()  argument
1790 void rd_train(struct mrc_params *mrc_params)  in rd_train()  argument
1795 	uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;  in rd_train()
1826 		if (mrc_params->channel_enables & (1 << ch)) {  in rd_train()
1828 				if (mrc_params->rank_enables & (1 << rk)) {  in rd_train()
1841 		if (mrc_params->channel_enables & (1 << ch)) {  in rd_train()
1843 				if (mrc_params->rank_enables & (1 << rk)) {  in rd_train()
1864 	bl_mask = byte_lane_mask(mrc_params);  in rd_train()
1879 				if (mrc_params->channel_enables & (0x1 << ch)) {  in rd_train()
1881 						if (mrc_params->rank_enables &  in rd_train()
1897 							mrc_params->hte_setup = 1;  in rd_train()
1902 								result = check_bls_ex(mrc_params, address);  in rd_train()
1963 		if (mrc_params->channel_enables & (1 << ch)) {  in rd_train()
1965 				if (mrc_params->rank_enables & (1 << rk)) {  in rd_train()
2015 				if (mrc_params->channel_enables & (1 << ch)) {  in rd_train()
2017 						if (mrc_params->rank_enables & (1 << rk)) {  in rd_train()
2035 			mrc_params->hte_setup = 1;  in rd_train()
2038 			if (check_bls_ex(mrc_params, address) & 0xff) {  in rd_train()
2050 		if (mrc_params->channel_enables & (1 << ch)) {  in rd_train()
2052 				if (mrc_params->rank_enables & (1 << rk)) {  in rd_train()
2088 void wr_train(struct mrc_params *mrc_params)  in wr_train()  argument
2093 	uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;  in wr_train()
2118 		if (mrc_params->channel_enables & (1 << ch)) {  in wr_train()
2120 				if (mrc_params->rank_enables & (1 << rk)) {  in wr_train()
2133 		if (mrc_params->channel_enables & (1 << ch)) {  in wr_train()
2135 				if (mrc_params->rank_enables & (1 << rk)) {  in wr_train()
2154 	bl_mask = byte_lane_mask(mrc_params);  in wr_train()
2171 			if (mrc_params->channel_enables & (1 << ch)) {  in wr_train()
2173 					if (mrc_params->rank_enables &  in wr_train()
2187 			if (mrc_params->channel_enables & (1 << ch)) {  in wr_train()
2189 					if (mrc_params->rank_enables &  in wr_train()
2195 						mrc_params->hte_setup = 1;  in wr_train()
2200 							result = check_bls_ex(mrc_params, address);  in wr_train()
2241 		if (mrc_params->channel_enables & (1 << ch)) {  in wr_train()
2243 				if (mrc_params->rank_enables & (1 << rk)) {  in wr_train()
2280 void store_timings(struct mrc_params *mrc_params)  in store_timings()  argument
2283 	struct mrc_timings *mt = &mrc_params->timings;  in store_timings()
2304 	mt->ddr_speed = mrc_params->ddr_speed;  in store_timings()
2311 void enable_scrambling(struct mrc_params *mrc_params)  in enable_scrambling()  argument
2316 	if (mrc_params->scrambling_enables == 0)  in enable_scrambling()
2322 	lfsr = mrc_params->timings.scrambler_seed;  in enable_scrambling()
2324 	if (mrc_params->boot_mode == BM_COLD) {  in enable_scrambling()
2347 		mrc_params->timings.scrambler_seed = lfsr;  in enable_scrambling()
2367 void prog_ddr_control(struct mrc_params *mrc_params)  in prog_ddr_control()  argument
2380 	dpmc0 |= (mrc_params->power_down_disable << 25);  in prog_ddr_control()
2397 void prog_dra_drb(struct mrc_params *mrc_params)  in prog_dra_drb()  argument
2401 	u8 density = mrc_params->params.density;  in prog_dra_drb()
2410 	if (mrc_params->rank_enables & 1)  in prog_dra_drb()
2412 	if (mrc_params->rank_enables & 2)  in prog_dra_drb()
2414 	if (mrc_params->dram_width == X16) {  in prog_dra_drb()
2430 	drp |= (mrc_params->address_mode << 14);  in prog_dra_drb()
2442 void perform_wake(struct mrc_params *mrc_params)  in perform_wake()  argument
2455 void change_refresh_period(struct mrc_params *mrc_params)  in change_refresh_period()  argument
2465 	drfc |= (mrc_params->refresh_rate << 12);  in change_refresh_period()
2485 void set_auto_refresh(struct mrc_params *mrc_params)  in set_auto_refresh()  argument
2500 		if (mrc_params->channel_enables & (1 << channel)) {  in set_auto_refresh()
2505 			switch (mrc_params->rd_odt_value) {  in set_auto_refresh()
2532 				if (mrc_params->rank_enables & (1 << rank))  in set_auto_refresh()
2549 void ecc_enable(struct mrc_params *mrc_params)  in ecc_enable()  argument
2555 	if (mrc_params->ecc_enables == 0)  in ecc_enable()
2577 	mrc_params->mem_size -= mrc_params->mem_size / 8;  in ecc_enable()
2580 	if (mrc_params->boot_mode != BM_S3) {  in ecc_enable()
2582 		hte_mem_init(mrc_params, MRC_MEM_INIT);  in ecc_enable()
2593 void memory_test(struct mrc_params *mrc_params)  in memory_test()  argument
2600 	result = hte_mem_init(mrc_params, MRC_MEM_TEST);  in memory_test()
2604 	mrc_params->status = ((result == 0) ? MRC_SUCCESS : MRC_E_MEMTEST);  in memory_test()
2609 void lock_registers(struct mrc_params *mrc_params)  in lock_registers()  argument