Lines Matching refs:dtr0
74 u32 dtr0, dtr1, dtr2, dtr3, dtr4; in prog_ddr_timing_control() local
82 dtr0 = msg_port_read(MEM_CTLR, DTR0); in prog_ddr_timing_control()
104 dtr0 &= ~DTR0_DFREQ_MASK; in prog_ddr_timing_control()
105 dtr0 |= mrc_params->ddr_speed; in prog_ddr_timing_control()
106 dtr0 &= ~DTR0_TCL_MASK; in prog_ddr_timing_control()
108 dtr0 |= ((tcl - 5) << 12); in prog_ddr_timing_control()
109 dtr0 &= ~DTR0_TRP_MASK; in prog_ddr_timing_control()
110 dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */ in prog_ddr_timing_control()
111 dtr0 &= ~DTR0_TRCD_MASK; in prog_ddr_timing_control()
112 dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */ in prog_ddr_timing_control()
172 msg_port_write(MEM_CTLR, DTR0, dtr0); in prog_ddr_timing_control()
1158 u32 dtr0; in perform_jedec_init() local
1180 dtr0 = msg_port_read(MEM_CTLR, DTR0); in perform_jedec_init()
1298 mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10); in perform_jedec_init()