Lines Matching refs:ch
261 uint8_t ch; /* channel counter */ in ddrphy_init() local
285 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
286 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
289 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
293 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
297 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
309 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
310 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
319 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
342 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
348 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
373 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
395 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
401 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
419 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
425 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
434 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
440 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
448 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
453 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
460 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
465 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
473 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
480 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
487 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
493 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
499 CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
504 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
509 CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
516 CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
524 CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
528 CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
532 CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
536 CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
540 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
545 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
550 CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
554 CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
558 CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
562 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
573 DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
577 CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
581 CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
585 DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
589 CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
594 COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
600 DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
604 DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
608 CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
621 DLYSELCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
625 TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
630 CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
635 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
642 DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
647 DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
652 DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
657 DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
662 DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
667 DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
672 DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
676 DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
682 DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
687 DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
692 DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
697 DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
702 DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
707 DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
712 DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
716 DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
722 CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
727 CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
732 CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
737 CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
742 CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
747 CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
752 CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
756 CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
762 CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
767 CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
772 CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
777 CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
784 CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
789 CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
794 CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
799 CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
806 DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
811 DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
818 DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
823 DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
830 CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
835 CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
842 set_wcmd(ch, ddr_wcmd[PLATFORM_ID]); in ddrphy_init()
844 set_wcmd(ch, ddr_wclk[PLATFORM_ID] + HALF_CLK); in ddrphy_init()
849 set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]); in ddrphy_init()
851 set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]); in ddrphy_init()
853 set_wctl(ch, rk, ddr_wclk[PLATFORM_ID] + HALF_CLK); in ddrphy_init()
940 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
941 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
949 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
961 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
966 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
976 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
977 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
985 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
997 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1002 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1012 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1013 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
1029 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1036 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1043 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1055 CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1064 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1065 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
1074 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1080 ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1083 CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1086 CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1089 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1096 CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1102 CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1108 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1111 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & in ddrphy_init()
1118 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1124 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
1133 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
1140 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1145 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1359 uint8_t ch, rk, bl; in restore_timings() local
1362 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1365 set_rcvn(ch, rk, bl, mt->rcvn[ch][rk][bl]); in restore_timings()
1366 set_rdqs(ch, rk, bl, mt->rdqs[ch][rk][bl]); in restore_timings()
1367 set_wdqs(ch, rk, bl, mt->wdqs[ch][rk][bl]); in restore_timings()
1368 set_wdq(ch, rk, bl, mt->wdq[ch][rk][bl]); in restore_timings()
1371 set_vref(ch, bl, mt->vref[ch][bl]); in restore_timings()
1374 set_wctl(ch, rk, mt->wctl[ch][rk]); in restore_timings()
1376 set_wcmd(ch, mt->wcmd[ch]); in restore_timings()
1388 uint8_t ch, rk, bl; in default_timings() local
1390 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1393 set_rdqs(ch, rk, bl, 24); in default_timings()
1396 set_vref(ch, bl, 32); in default_timings()
1410 uint8_t ch; /* channel counter */ in rcvn_cal() local
1451 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
1452 if (mrc_params->channel_enables & (1 << ch)) { in rcvn_cal()
1460 mrc_post_code(0x05, 0x10 + ((ch << 4) | rk)); in rcvn_cal()
1465 set_rcvn(ch, rk, bl, ddr_rcvn[PLATFORM_ID]); in rcvn_cal()
1472 ch * DDRIODQ_CH_OFFSET, in rcvn_cal()
1480 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1484 find_rising_edge(mrc_params, delay, ch, rk, true); in rcvn_cal()
1489 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1493 temp = sample_dqs(mrc_params, ch, rk, true); in rcvn_cal()
1498 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1501 training_message(ch, rk, bl); in rcvn_cal()
1515 final_delay[ch][bl] += delay[bl]; in rcvn_cal()
1517 set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rcvn_cal()
1523 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1532 ch * DDRIODQ_CH_OFFSET, in rcvn_cal()
1557 uint8_t ch; /* channel counter */ in wr_level() local
1597 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_level()
1598 if (mrc_params->channel_enables & (1 << ch)) { in wr_level()
1606 mrc_post_code(0x06, 0x10 + ((ch << 4) | rk)); in wr_level()
1610 set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); in wr_level()
1611 set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); in wr_level()
1642 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1649 CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, in wr_level()
1658 delay[bl] = get_wclk(ch, rk); in wr_level()
1660 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1664 find_rising_edge(mrc_params, delay, ch, rk, false); in wr_level()
1668 CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, in wr_level()
1674 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1694 mrc_post_code(0x06, 0x30 + ((ch << 4) | rk)); in wr_level()
1706 delay[bl] = get_wdqs(ch, rk, bl) + FULL_CLK; in wr_level()
1707 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1712 set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); in wr_level()
1716 address = get_addr(ch, rk); in wr_level()
1731 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1733 set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); in wr_level()
1743 final_delay[ch][bl] += delay[bl]; in wr_level()
1744 set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in wr_level()
1746 set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); in wr_level()
1792 uint8_t ch; /* channel counter */ in rd_train() local
1825 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1826 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1832 set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); in rd_train()
1840 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1841 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1848 x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; in rd_train()
1849 x_coordinate[R][B][ch][rk][bl] = RDQS_MAX; in rd_train()
1850 x_coordinate[L][T][ch][rk][bl] = RDQS_MIN; in rd_train()
1851 x_coordinate[R][T][ch][rk][bl] = RDQS_MAX; in rd_train()
1853 y_coordinate[L][B][ch][bl] = VREF_MIN; in rd_train()
1854 y_coordinate[R][B][ch][bl] = VREF_MIN; in rd_train()
1855 y_coordinate[L][T][ch][bl] = VREF_MAX; in rd_train()
1856 y_coordinate[R][T][ch][bl] = VREF_MAX; in rd_train()
1878 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1879 if (mrc_params->channel_enables & (0x1 << ch)) { in rd_train()
1887 set_rdqs(ch, rk, bl, in rd_train()
1888 x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1889 set_vref(ch, bl, in rd_train()
1890 y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1894 address = get_addr(ch, rk); in rd_train()
1912 x_coordinate[L][side_y][ch][rk][bl] += RDQS_STEP; in rd_train()
1914 x_coordinate[R][side_y][ch][rk][bl] -= RDQS_STEP; in rd_train()
1917 if ((x_coordinate[L][side_y][ch][rk][bl] > (RDQS_MAX - MIN_RDQS_EYE)) || in rd_train()
1918 (x_coordinate[R][side_y][ch][rk][bl] < (RDQS_MIN + MIN_RDQS_EYE)) || in rd_train()
1919 (x_coordinate[L][side_y][ch][rk][bl] == in rd_train()
1920 x_coordinate[R][side_y][ch][rk][bl])) { in rd_train()
1926 y_coordinate[side_x][B][ch][bl] += VREF_STEP; in rd_train()
1928 y_coordinate[side_x][T][ch][bl] -= VREF_STEP; in rd_train()
1931 if ((y_coordinate[side_x][B][ch][bl] > (VREF_MAX - MIN_VREF_EYE)) || in rd_train()
1932 (y_coordinate[side_x][T][ch][bl] < (VREF_MIN + MIN_VREF_EYE)) || in rd_train()
1933 (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { in rd_train()
1935 training_message(ch, rk, bl); in rd_train()
1939 set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1941 x_coordinate[side_x][side_y][ch][rk][bl] = in rd_train()
1947 set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1962 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1963 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1974 x_coordinate[L][T][ch][rk][bl], in rd_train()
1975 x_coordinate[R][T][ch][rk][bl], in rd_train()
1976 x_coordinate[L][B][ch][rk][bl], in rd_train()
1977 x_coordinate[R][B][ch][rk][bl]); in rd_train()
1980 temp1 = (x_coordinate[R][T][ch][rk][bl] + x_coordinate[L][T][ch][rk][bl]) / 2; in rd_train()
1982 temp2 = (x_coordinate[R][B][ch][rk][bl] + x_coordinate[L][B][ch][rk][bl]) / 2; in rd_train()
1984 x_center[ch][rk][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
1990 y_coordinate[R][B][ch][bl], in rd_train()
1991 y_coordinate[R][T][ch][bl], in rd_train()
1992 y_coordinate[L][B][ch][bl], in rd_train()
1993 y_coordinate[L][T][ch][bl]); in rd_train()
1996 temp1 = (y_coordinate[R][T][ch][bl] + y_coordinate[R][B][ch][bl]) / 2; in rd_train()
1998 temp2 = (y_coordinate[L][T][ch][bl] + y_coordinate[L][B][ch][bl]) / 2; in rd_train()
2000 y_center[ch][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
2014 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
2015 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
2020 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); in rd_train()
2022 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); in rd_train()
2025 set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); in rd_train()
2027 set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); in rd_train()
2049 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
2050 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
2060 final_delay[ch][bl] += x_center[ch][rk][bl]; in rd_train()
2061 set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rd_train()
2063 set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); in rd_train()
2066 set_vref(ch, bl, y_center[ch][bl]); in rd_train()
2090 uint8_t ch; /* channel counter */ in wr_train() local
2117 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2118 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2124 set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); in wr_train()
2132 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2133 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2144 temp = get_wdqs(ch, rk, bl) - QRTR_CLK; in wr_train()
2145 delay[L][ch][rk][bl] = temp - QRTR_CLK; in wr_train()
2146 delay[R][ch][rk][bl] = temp + QRTR_CLK; in wr_train()
2170 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2171 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2178 set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); in wr_train()
2186 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2187 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2192 address = get_addr(ch, rk); in wr_train()
2208 delay[L][ch][rk][bl] += WDQ_STEP; in wr_train()
2210 delay[R][ch][rk][bl] -= WDQ_STEP; in wr_train()
2213 if (delay[L][ch][rk][bl] != delay[R][ch][rk][bl]) { in wr_train()
2218 set_wdq(ch, rk, bl, in wr_train()
2219 delay[side][ch][rk][bl]); in wr_train()
2225 training_message(ch, rk, bl); in wr_train()
2240 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2241 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2252 delay[L][ch][rk][bl], in wr_train()
2253 delay[R][ch][rk][bl]); in wr_train()
2255 temp = (delay[R][ch][rk][bl] + delay[L][ch][rk][bl]) / 2; in wr_train()
2258 final_delay[ch][bl] += temp; in wr_train()
2259 set_wdq(ch, rk, bl, in wr_train()
2260 final_delay[ch][bl] / num_ranks_enabled); in wr_train()
2262 set_wdq(ch, rk, bl, temp); in wr_train()
2282 uint8_t ch, rk, bl; in store_timings() local
2285 for (ch = 0; ch < NUM_CHANNELS; ch++) { in store_timings()
2288 mt->rcvn[ch][rk][bl] = get_rcvn(ch, rk, bl); in store_timings()
2289 mt->rdqs[ch][rk][bl] = get_rdqs(ch, rk, bl); in store_timings()
2290 mt->wdqs[ch][rk][bl] = get_wdqs(ch, rk, bl); in store_timings()
2291 mt->wdq[ch][rk][bl] = get_wdq(ch, rk, bl); in store_timings()
2294 mt->vref[ch][bl] = get_vref(ch, bl); in store_timings()
2297 mt->wctl[ch][rk] = get_wctl(ch, rk); in store_timings()
2300 mt->wcmd[ch] = get_wcmd(ch); in store_timings()