Lines Matching full:bl
1282 * BIT[01:00] --> BL: want "8 Fixed" (0) in perform_jedec_init()
1359 uint8_t ch, rk, bl; in restore_timings() local
1364 for (bl = 0; bl < NUM_BYTE_LANES; bl++) { in restore_timings()
1365 set_rcvn(ch, rk, bl, mt->rcvn[ch][rk][bl]); in restore_timings()
1366 set_rdqs(ch, rk, bl, mt->rdqs[ch][rk][bl]); in restore_timings()
1367 set_wdqs(ch, rk, bl, mt->wdqs[ch][rk][bl]); in restore_timings()
1368 set_wdq(ch, rk, bl, mt->wdq[ch][rk][bl]); in restore_timings()
1371 set_vref(ch, bl, mt->vref[ch][bl]); in restore_timings()
1388 uint8_t ch, rk, bl; in default_timings() local
1392 for (bl = 0; bl < NUM_BYTE_LANES; bl++) { in default_timings()
1393 set_rdqs(ch, rk, bl, 24); in default_timings()
1396 set_vref(ch, bl, 32); in default_timings()
1412 uint8_t bl; /* byte lane counter */ in rcvn_cal() local
1464 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) in rcvn_cal()
1465 set_rcvn(ch, rk, bl, ddr_rcvn[PLATFORM_ID]); in rcvn_cal()
1468 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { in rcvn_cal()
1471 (bl >> 1) * DDRIODQ_BL_OFFSET + in rcvn_cal()
1476 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in rcvn_cal()
1478 delay[bl] = (4 + 1) * FULL_CLK; in rcvn_cal()
1480 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1487 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in rcvn_cal()
1488 delay[bl] += QRTR_CLK; in rcvn_cal()
1489 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1494 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in rcvn_cal()
1495 if (temp & (1 << bl)) { in rcvn_cal()
1496 if (delay[bl] >= FULL_CLK) { in rcvn_cal()
1497 delay[bl] -= FULL_CLK; in rcvn_cal()
1498 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1501 training_message(ch, rk, bl); in rcvn_cal()
1512 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in rcvn_cal()
1513 delay[bl] += QRTR_CLK; in rcvn_cal()
1515 final_delay[ch][bl] += delay[bl]; in rcvn_cal()
1517 set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rcvn_cal()
1521 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in rcvn_cal()
1522 delay[bl] += QRTR_CLK; in rcvn_cal()
1523 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1528 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { in rcvn_cal()
1531 (bl >> 1) * DDRIODQ_BL_OFFSET + in rcvn_cal()
1559 uint8_t bl; /* byte lane counter */ in wr_level() local
1609 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in wr_level()
1610 set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); in wr_level()
1611 set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); in wr_level()
1636 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { in wr_level()
1642 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1653 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in wr_level()
1658 delay[bl] = get_wclk(ch, rk); in wr_level()
1660 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1671 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { in wr_level()
1674 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1705 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in wr_level()
1706 delay[bl] = get_wdqs(ch, rk, bl) + FULL_CLK; in wr_level()
1707 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1712 set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); in wr_level()
1727 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in wr_level()
1728 if (coarse_result & (coarse_result_mask << bl)) { in wr_level()
1730 delay[bl] -= FULL_CLK; in wr_level()
1731 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1733 set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); in wr_level()
1742 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in wr_level()
1743 final_delay[ch][bl] += delay[bl]; in wr_level()
1744 set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in wr_level()
1746 set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); in wr_level()
1794 uint8_t bl; /* byte lane counter */ in rd_train() local
1829 for (bl = 0; in rd_train()
1830 bl < NUM_BYTE_LANES / bl_divisor; in rd_train()
1831 bl++) { in rd_train()
1832 set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); in rd_train()
1844 for (bl = 0; in rd_train()
1845 bl < NUM_BYTE_LANES / bl_divisor; in rd_train()
1846 bl++) { in rd_train()
1848 x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; in rd_train()
1849 x_coordinate[R][B][ch][rk][bl] = RDQS_MAX; in rd_train()
1850 x_coordinate[L][T][ch][rk][bl] = RDQS_MIN; in rd_train()
1851 x_coordinate[R][T][ch][rk][bl] = RDQS_MAX; in rd_train()
1853 y_coordinate[L][B][ch][bl] = VREF_MIN; in rd_train()
1854 y_coordinate[R][B][ch][bl] = VREF_MIN; in rd_train()
1855 y_coordinate[L][T][ch][bl] = VREF_MAX; in rd_train()
1856 y_coordinate[R][T][ch][bl] = VREF_MAX; in rd_train()
1884 for (bl = 0; in rd_train()
1885 bl < NUM_BYTE_LANES / bl_divisor; in rd_train()
1886 bl++) { in rd_train()
1887 set_rdqs(ch, rk, bl, in rd_train()
1888 x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1889 set_vref(ch, bl, in rd_train()
1890 y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1907 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in rd_train()
1909 (bl_mask << bl)) { in rd_train()
1912 x_coordinate[L][side_y][ch][rk][bl] += RDQS_STEP; in rd_train()
1914 x_coordinate[R][side_y][ch][rk][bl] -= RDQS_STEP; in rd_train()
1917 if ((x_coordinate[L][side_y][ch][rk][bl] > (RDQS_MAX - MIN_RDQS_EYE)) || in rd_train()
1918 (x_coordinate[R][side_y][ch][rk][bl] < (RDQS_MIN + MIN_RDQS_EYE)) || in rd_train()
1919 (x_coordinate[L][side_y][ch][rk][bl] == in rd_train()
1920 x_coordinate[R][side_y][ch][rk][bl])) { in rd_train()
1926 y_coordinate[side_x][B][ch][bl] += VREF_STEP; in rd_train()
1928 y_coordinate[side_x][T][ch][bl] -= VREF_STEP; in rd_train()
1931 if ((y_coordinate[side_x][B][ch][bl] > (VREF_MAX - MIN_VREF_EYE)) || in rd_train()
1932 (y_coordinate[side_x][T][ch][bl] < (VREF_MIN + MIN_VREF_EYE)) || in rd_train()
1933 (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { in rd_train()
1935 training_message(ch, rk, bl); in rd_train()
1939 set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1941 x_coordinate[side_x][side_y][ch][rk][bl] = in rd_train()
1947 set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1966 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in rd_train()
1973 rk, bl, in rd_train()
1974 x_coordinate[L][T][ch][rk][bl], in rd_train()
1975 x_coordinate[R][T][ch][rk][bl], in rd_train()
1976 x_coordinate[L][B][ch][rk][bl], in rd_train()
1977 x_coordinate[R][B][ch][rk][bl]); in rd_train()
1980 temp1 = (x_coordinate[R][T][ch][rk][bl] + x_coordinate[L][T][ch][rk][bl]) / 2; in rd_train()
1982 temp2 = (x_coordinate[R][B][ch][rk][bl] + x_coordinate[L][B][ch][rk][bl]) / 2; in rd_train()
1984 x_center[ch][rk][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
1989 bl, in rd_train()
1990 y_coordinate[R][B][ch][bl], in rd_train()
1991 y_coordinate[R][T][ch][bl], in rd_train()
1992 y_coordinate[L][B][ch][bl], in rd_train()
1993 y_coordinate[L][T][ch][bl]); in rd_train()
1996 temp1 = (y_coordinate[R][T][ch][bl] + y_coordinate[R][B][ch][bl]) / 2; in rd_train()
1998 temp2 = (y_coordinate[L][T][ch][bl] + y_coordinate[L][B][ch][bl]) / 2; in rd_train()
2000 y_center[ch][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
2018 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in rd_train()
2020 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); in rd_train()
2022 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); in rd_train()
2025 set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); in rd_train()
2027 set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); in rd_train()
2057 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in rd_train()
2060 final_delay[ch][bl] += x_center[ch][rk][bl]; in rd_train()
2061 set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rd_train()
2063 set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); in rd_train()
2066 set_vref(ch, bl, y_center[ch][bl]); in rd_train()
2092 uint8_t bl; /* byte lane counter */ in wr_train() local
2121 for (bl = 0; in wr_train()
2122 bl < NUM_BYTE_LANES / bl_divisor; in wr_train()
2123 bl++) { in wr_train()
2124 set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); in wr_train()
2136 for (bl = 0; in wr_train()
2137 bl < NUM_BYTE_LANES / bl_divisor; in wr_train()
2138 bl++) { in wr_train()
2144 temp = get_wdqs(ch, rk, bl) - QRTR_CLK; in wr_train()
2145 delay[L][ch][rk][bl] = temp - QRTR_CLK; in wr_train()
2146 delay[R][ch][rk][bl] = temp + QRTR_CLK; in wr_train()
2163 * start algorithm on the LEFT side and train each channel/bl in wr_train()
2175 for (bl = 0; in wr_train()
2176 bl < NUM_BYTE_LANES / bl_divisor; in wr_train()
2177 bl++) { in wr_train()
2178 set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); in wr_train()
2204 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in wr_train()
2206 (bl_mask << bl)) { in wr_train()
2208 delay[L][ch][rk][bl] += WDQ_STEP; in wr_train()
2210 delay[R][ch][rk][bl] -= WDQ_STEP; in wr_train()
2213 if (delay[L][ch][rk][bl] != delay[R][ch][rk][bl]) { in wr_train()
2218 set_wdq(ch, rk, bl, in wr_train()
2219 delay[side][ch][rk][bl]); in wr_train()
2225 training_message(ch, rk, bl); in wr_train()
2248 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in wr_train()
2251 rk, bl, in wr_train()
2252 delay[L][ch][rk][bl], in wr_train()
2253 delay[R][ch][rk][bl]); in wr_train()
2255 temp = (delay[R][ch][rk][bl] + delay[L][ch][rk][bl]) / 2; in wr_train()
2258 final_delay[ch][bl] += temp; in wr_train()
2259 set_wdq(ch, rk, bl, in wr_train()
2260 final_delay[ch][bl] / num_ranks_enabled); in wr_train()
2262 set_wdq(ch, rk, bl, temp); in wr_train()
2282 uint8_t ch, rk, bl; in store_timings() local
2287 for (bl = 0; bl < NUM_BYTE_LANES; bl++) { in store_timings()
2288 mt->rcvn[ch][rk][bl] = get_rcvn(ch, rk, bl); in store_timings()
2289 mt->rdqs[ch][rk][bl] = get_rdqs(ch, rk, bl); in store_timings()
2290 mt->wdqs[ch][rk][bl] = get_wdqs(ch, rk, bl); in store_timings()
2291 mt->wdq[ch][rk][bl] = get_wdq(ch, rk, bl); in store_timings()
2294 mt->vref[ch][bl] = get_vref(ch, bl); in store_timings()
2489 uint32_t bl; in set_auto_refresh() local
2514 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { in set_auto_refresh()
2517 B0OVRCTL + bl * DDRIODQ_BL_OFFSET + in set_auto_refresh()
2524 B1OVRCTL + bl * DDRIODQ_BL_OFFSET + in set_auto_refresh()